| commit | fe2dc61b9a585bffa67025893f5c731d143548f0 | [log] [tgz] |
|---|---|---|
| author | Matthew Blecker <matthewb@chromium.org> | Thu Aug 12 00:23:12 2021 -0700 |
| committer | Commit Bot <commit-bot@chromium.org> | Tue Aug 24 05:36:07 2021 +0000 |
| tree | 596cedf040a6c990b68abe996545ce58dccc406f | |
| parent | 5634d7596e87f6455f5365b04243d585bca6aa59 [diff] |
mb/google/poppy/variants/atlas: stop setting touchscreen probed=1
All Atlas devices have the touchscreen controller, so probing for its
presence is unnecessary. Removing the probe requirement allows the
touchscreen ACPI device in Linux to re-enumerate when rebinding its
I2C adapter device.
Without this change, after rebinding the touchscreen's I2C adapter
device using sysfs the touchscreen ACPI and HID devices are absent, and
the touchscreen is unresponsive.
With this change, the touchscreen ACPI and HID devices are re-created
after rebinding its I2C adapter device, and the touchscreen becomes
responsive again.
BUG=b:177350937
TEST=Tested on 2 Atlas DUTs running Chrome OS R94 top-of-tree builds
with Linux 4.4 and 5.4.
Built new AP FW from Atlas Chrome OS firmware branch with this change
applied. Tested shipping RO + new RW, and new RO + new RW.
Test sequence:
1) Boot DUT, verify basic touchscreen functionality.
2) $ cd /sys/bus/platform/drivers/i2c_designware
3) $ ls -ld i2c_designware.0{,/i2c-6{,/i2c-ACPI0C50:00{,/0018:0483:1058.*{,/hidraw{,/hidraw*}}}}}
lrwxrwxrwx. 1 root root 0 Aug 12 01:07 i2c_designware.0 -> ../../../../devices/pci0000:00/0000:00:15.0/i2c_designware.0
drwxr-xr-x. 5 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6
drwxr-xr-x. 4 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00
drwxr-xr-x. 5 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0002
drwxr-xr-x. 3 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0002/hidraw
drwxr-xr-x. 3 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0002/hidraw/hidraw1
4) $ echo i2c_designware.0 > unbind
5) Verify touchscreen is unresponsive (as expected after unbind).
6) $ ls -ld i2c_designware.0
ls: cannot access 'i2c_designware.0': No such file or directory
7) $ echo i2c_designware.0 > bind
*** Without this change: ***
8) Touchscreen remains unresponsive.
9) $ ls -ld i2c_designware.0{,/i2c-6{,/i2c-ACPI0C50:00}}
ls: cannot access 'i2c_designware.0/i2c-6/i2c-ACPI0C50:00': No such file or directory
lrwxrwxrwx. 1 root root 0 Aug 12 01:18 i2c_designware.0 -> ../../../../devices/pci0000:00/0000:00:15.0/i2c_designware.0
drwxr-xr-x. 4 root root 0 Aug 12 01:18 i2c_designware.0/i2c-6
*** With this change: ***
8) Touchscreen is functional again.
9) $ ls -ld i2c_designware.0{,/i2c-6{,/i2c-ACPI0C50:00{,/0018:0483:1058.*{,/hidraw{,/hidraw*}}}}}
lrwxrwxrwx. 1 root root 0 Aug 12 01:09 i2c_designware.0 -> ../../../../devices/pci0000:00/0000:00:15.0/i2c_designware.0
drwxr-xr-x. 5 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6
drwxr-xr-x. 4 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00
drwxr-xr-x. 5 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0003
drwxr-xr-x. 3 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0003/hidraw
drwxr-xr-x. 3 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0003/hidraw/hidraw1
Signed-off-by: Matthew Blecker <matthewb@chromium.org>
Change-Id: I7b90690b0591e8748d7a007f8cc9688d393e59db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56928
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GitOrigin-RevId: a5714574fd0b8f93366b813c356422873aac989f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3098026
Tested-by: Copybara Service <copybara-worker-blackhole@google.com>
Tested-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Commit-Queue: Rob Barnes <robbarnes@google.com>
(cherry picked from commit f839b361e6f08940b6044e95175059d29499aaac)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3115669
Reviewed-by: caveh jalali <caveh@chromium.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig and make nconfig)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.