commit | 04607daf330c904798a9120a60b348007a68095a | [log] [tgz] |
---|---|---|
author | Edward O'Callaghan <quasisec@google.com> | Fri Aug 14 12:27:42 2020 +1000 |
committer | Commit Bot <commit-bot@chromium.org> | Sat Aug 22 04:44:15 2020 +0000 |
tree | 3082a061855a917981162253ce4d20de0cf91818 | |
parent | bb039b73603f7042ca131b2b444a9fac5d5f648a [diff] |
UPSTREAM: mb/google/puff: Select cse_board_reset() strong symbol Since Puff uses CSE Lite SKU that supports in-field CSME updates an additional reset is triggered when jmp from RO to RW during boot. However this reset is not detected by the cr50 running older firmware because the strapping configuration for EFS2 uses PLT_RST_L to assert to cr50 that a AP reset occured. The older cr50 firmware version of 0.0.22 only monitors AP resets via SYS_RESET_L and hence never detects the reset. To mitigate the issue above a modified reset sequence is required to be performed to signal the reset occured and hence a board-specific cse_board_reset() strong symbol is provided to modify the flow accordingly. V.2: Select CHROMEOS_CSE_BOARD_RESET_OVERRIDE common implementation instead of a local variant in mainboard.c BUG=b:162290856 BRANCH=puff TEST=none Signed-off-by: Edward O'Callaghan <quasisec@google.com> Original-Commit-Id: bd409ad69f6f33681bc5cde65cc72eedbd8d2abc Original-Change-Id: I27ab9711aedf92b5af7a58f3b5472ce79f78c8fa Original-Signed-off-by: Edward O'Callaghan <quasisec@google.com> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/44454 Original-Reviewed-by: Sam McNally <sammc@google.com> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Change-Id: I98b5e803fc4ae852b4a7f9623c2f4c96e4204594 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2369086 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Commit-Queue: Edward O'Callaghan <quasisec@chromium.org> Tested-by: Edward O'Callaghan <quasisec@chromium.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.