UPSTREAM: soc/intel/apollolake: Bypass FSP's CpuMemorytest, PCIe pwr seq & SPI Init
CpuMemoryTest in FSP tests 0 to 1M of the RAM after MRC init. With
PAGING_IN_CACHE_AS_RAM enabled for GLK, there was no page table
entry for this range which caused a page fault. Since this test
is anyway not exhaustive, we will skip the memory test in FSP.
There is an option to do PCIe power sequence from within FSP if provided
with the GPIOs used for PERST to FSP. Since we do this from coreboot,
will skip the PCIe power sequence done by FSP.
FSP does not know what the clock requirements are for the device on
SPI bus, hence it should not modify what coreboot has set up. Hence
skipping SPI clock programming in FSP.
CQ-DEPEND=CL:*627827
BUG=b:78599939, b:78599576, b:76058338
BRANCH=None
TEST=Build coreboot for Octopus board.
Change-Id: I468654553c41ed2c8b981e4d5db316a37c4e7bd2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Commit-Id: 5af546c5e40835145fee6eff4f43283bea80db91
Original-Change-Id: I4fa7a73fbb4676bb7af2416c8a33bf10ef41dd53
Original-Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/26284
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/1069942
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2 files changed
