diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index d63e500..628781f 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -95,6 +95,7 @@
 	default "Jinlon" if BOARD_GOOGLE_JINLON
 	default "Kindred" if BOARD_GOOGLE_KINDRED
 	default "Kohaku" if BOARD_GOOGLE_KOHAKU
+	default "Nightfury" if BOARD_GOOGLE_NIGHTFURY
 	default "Puff" if BOARD_GOOGLE_PUFF
 	default "Stryke" if BOARD_GOOGLE_STRYKE
 
@@ -125,6 +126,7 @@
 	default "jinlon" if BOARD_GOOGLE_JINLON
 	default "kindred" if BOARD_GOOGLE_KINDRED
 	default "kohaku" if BOARD_GOOGLE_KOHAKU
+	default "nightfury" if BOARD_GOOGLE_NIGHTFURY
 	default "puff" if BOARD_GOOGLE_PUFF
 	default "stryke" if BOARD_GOOGLE_STRYKE
 
diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name
index ed90de6..b0fbf37 100644
--- a/src/mainboard/google/hatch/Kconfig.name
+++ b/src/mainboard/google/hatch/Kconfig.name
@@ -38,6 +38,11 @@
 	select CHROMEOS_DSM_CALIB
 	select DRIVERS_I2C_RT1011
 
+config BOARD_GOOGLE_NIGHTFURY
+	bool "-> Nightfury"
+	select BOARD_GOOGLE_BASEBOARD_HATCH
+	select BOARD_ROMSIZE_KB_16384
+
 config BOARD_GOOGLE_PUFF
 	bool "-> Puff"
 	select BOARD_GOOGLE_BASEBOARD_HATCH
diff --git a/src/mainboard/google/hatch/variants/nightfury/Makefile.inc b/src/mainboard/google/hatch/variants/nightfury/Makefile.inc
new file mode 100644
index 0000000..09d0c22
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/nightfury/Makefile.inc
@@ -0,0 +1,23 @@
+## This file is part of the coreboot project.
+##
+## Copyright 2020 Google LLC
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+SPD_SOURCES = LP_8G_2133	# 0b000
+SPD_SOURCES += empty_ddr4	# 0b001
+SPD_SOURCES += LP_4G_2133	# 0b010
+
+romstage-y += memory.c
+
+bootblock-y += gpio.c
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/hatch/variants/nightfury/gpio.c b/src/mainboard/google/hatch/variants/nightfury/gpio.c
new file mode 100644
index 0000000..681f9ec
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/nightfury/gpio.c
@@ -0,0 +1,178 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+static const struct pad_config gpio_table[] = {
+	/* A18 :  NC */
+	PAD_NC(GPP_A18, NONE),
+	/* A19 :  NC */
+	PAD_NC(GPP_A19, NONE),
+	/* A20 :  NC */
+	PAD_NC(GPP_A20, NONE),
+	/* A22 :  NC */
+	PAD_NC(GPP_A22, NONE),
+	/* A23 :  NC */
+	PAD_NC(GPP_A23, NONE),
+
+	/* B8 :  NC */
+	PAD_NC(GPP_B8, NONE),
+	/* B20 :  NC */
+	PAD_NC(GPP_B20, NONE),
+	/* B21 :  NC */
+	PAD_NC(GPP_B21, NONE),
+	/* B22 :  NC */
+	PAD_NC(GPP_B22, NONE),
+
+	/* C1 : NC */
+	PAD_NC(GPP_C1, NONE),
+	/* C12 : EN_PP3300_TSP_DX */
+	PAD_CFG_GPO(GPP_C12, 0, DEEP),
+	/* C13 : EC_PCH_INT_L - needs to wake the system */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_C13, NONE, PLTRST, LEVEL, INVERT),
+	/* C23 : UART2_CTS# ==> NC */
+	PAD_NC(GPP_C23, NONE),
+
+	/* D16 : TOUCHSCREEN_INT_L */
+	PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT),
+
+	/* E4  : M2_SSD_PE_WAKE_ODL ==> NC */
+	PAD_NC(GPP_E4, NONE),
+	/* E5  : SATA_DEVSLP1 ==> NC */
+	PAD_NC(GPP_E5, NONE),
+
+	/* F1 : GPP_F1 ==> NC */
+	PAD_NC(GPP_F1, NONE),
+	/* F3  : MEM_STRAP_3 */
+	PAD_CFG_GPI(GPP_F3, NONE, PLTRST),
+	/* F10 : MEM_STRAP_2 */
+	PAD_CFG_GPI(GPP_F10, NONE, PLTRST),
+	/* F11 : EMMC_CMD ==> EMMC_CMD */
+	PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
+	/* F12 : EMMC_DATA0 ==> EMMC_DAT0 */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
+	/* F13 : EMMC_DATA1 ==> EMMC_DAT1 */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
+	/* F14 : EMMC_DATA2 ==> EMMC_DAT2 */
+	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
+	/* F15 : EMMC_DATA3 ==> EMMC_DAT3 */
+	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
+	/* F16 : EMMC_DATA4 ==> EMMC_DAT4 */
+	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
+	/* F17 : EMMC_DATA5 ==> EMMC_DAT5 */
+	PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
+	/* F18 : EMMC_DATA6 ==> EMMC_DAT6 */
+	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
+	/* F19 : EMMC_DATA7 ==> EMMC_DAT7 */
+	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+	/* F20 : EMMC_RCLK ==> EMMC_RCLK */
+	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+	/* F21 : EMMC_CLK ==> EMMC_CLK */
+	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+	/* F22 : EMMC_RESET# ==> EMMC_RST_L */
+	PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+
+	/* H3  : SPKR_PA_EN */
+	PAD_CFG_GPO(GPP_H3, 0, DEEP),
+	/* H4  : NC */
+	PAD_NC(GPP_H4, NONE),
+	/* H5  : NC */
+	PAD_NC(GPP_H5, NONE),
+	/* H19 : MEM_STRAP_0 */
+	PAD_CFG_GPI(GPP_H19, NONE, PLTRST),
+	/* H22 : MEM_STRAP_1 */
+	PAD_CFG_GPI(GPP_H22, NONE, PLTRST),
+};
+
+const struct pad_config *override_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+/*
+ * GPIOs configured before ramstage
+ * Note: the Hatch platform's romstage will configure
+ * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins
+ * as inputs before it reads them, so they are not
+ * needed in this table.
+ */
+static const struct pad_config early_gpio_table[] = {
+	/* B15 : H1_SLAVE_SPI_CS_L */
+	PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+	/* B16 : H1_SLAVE_SPI_CLK */
+	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
+	/* B17 : H1_SLAVE_SPI_MISO_R */
+	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+	/* B18 : H1_SLAVE_SPI_MOSI_R */
+	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+	/* C14 : BT_DISABLE_L */
+	PAD_CFG_GPO(GPP_C14, 0, DEEP),
+	/* PCH_WP_OD */
+	PAD_CFG_GPI(GPP_C20, NONE, DEEP),
+	/* C21 : H1_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
+	/* E1  : M2_SSD_PEDET */
+	PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
+	/* E5  : SATA_DEVSLP1 */
+	PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
+	/* F2  : MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_F2, NONE, PLTRST),
+	/* F3 : PCH_MEM_STRAP3 */
+	PAD_CFG_GPI(GPP_F3, NONE, PLTRST),
+	/* F10 : PCH_MEM_STRAP2 */
+	PAD_CFG_GPI(GPP_F10, NONE, PLTRST),
+	/* H19 : PCH_MEM_STRAP0 */
+	PAD_CFG_GPI(GPP_H19, NONE, PLTRST),
+	/* H22 : PCH_MEM_STRAP1 */
+	PAD_CFG_GPI(GPP_H22, NONE, PLTRST),
+};
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+/*
+ * Default GPIO settings before entering non-S5 sleep states.
+ * Configure A12: FPMCU_RST_ODL as GPO before entering sleep.
+ * This guarantees that A12's native3 function is disabled.
+ * See https://review.coreboot.org/c/coreboot/+/32111 .
+ */
+static const struct pad_config default_sleep_gpio_table[] = {
+
+};
+
+/*
+ * GPIO settings before entering S5, which are same as
+ * default_sleep_gpio_table but also, turn off FPMCU.
+ */
+static const struct pad_config s5_sleep_gpio_table[] = {
+
+};
+
+const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num)
+{
+	if (slp_typ == ACPI_S5) {
+		*num = ARRAY_SIZE(s5_sleep_gpio_table);
+		return s5_sleep_gpio_table;
+	}
+	*num = ARRAY_SIZE(default_sleep_gpio_table);
+	return default_sleep_gpio_table;
+}
diff --git a/src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl
new file mode 100644
index 0000000..edfad4b
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE	50
+#define DPTF_CPU_CRITICAL	105
+
+#define DPTF_TSR0_SENSOR_ID	0
+#define DPTF_TSR0_SENSOR_NAME	"Thermal Sensor - Charger"
+#define DPTF_TSR0_PASSIVE	45
+#define DPTF_TSR0_CRITICAL	90
+#define DPTF_TSR0_TABLET_PASSIVE        32
+#define DPTF_TSR0_TABLET_CRITICAL       90
+
+#define DPTF_TSR1_SENSOR_ID	1
+#define DPTF_TSR1_SENSOR_NAME	"Thermal Sensor - 5V"
+#define DPTF_TSR1_PASSIVE	45
+#define DPTF_TSR1_CRITICAL	90
+#define DPTF_TSR1_TABLET_PASSIVE        32
+#define DPTF_TSR1_TABLET_CRITICAL       90
+
+#define DPTF_TSR2_SENSOR_ID	2
+#define DPTF_TSR2_SENSOR_NAME	"Thermal Sensor - IA"
+#define DPTF_TSR2_PASSIVE	45
+#define DPTF_TSR2_CRITICAL	90
+#define DPTF_TSR2_TABLET_PASSIVE        32
+#define DPTF_TSR2_TABLET_CRITICAL       90
+
+#define DPTF_TSR3_SENSOR_ID	3
+#define DPTF_TSR3_SENSOR_NAME	"Thermal Sensor - GT"
+#define DPTF_TSR3_PASSIVE	45
+#define DPTF_TSR3_CRITICAL	90
+#define DPTF_TSR3_TABLET_PASSIVE        32
+#define DPTF_TSR3_TABLET_CRITICAL       90
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 },	/* 1.7A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
+})
+
+Name (DTRT, Package () {
+	/* CPU Throttle Effect on CPU */
+	Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 10, 0, 0, 0, 0 },
+
+	/* CPU Throttle Effect on 5V (TSR1) */
+	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 10, 0, 0, 0, 0 },
+
+	/* Charger Throttle Effect on Charger (TSR0) */
+	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 94, 0, 0, 0, 0 },
+
+	/* CPU Throttle Effect on IA (TSR2) */
+	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 10, 0, 0, 0, 0 },
+
+	/* CPU Throttle Effect on GT (TSR3) */
+	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR3, 100, 10, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+	0x2,		/* Revision */
+	Package () {	/* Power Limit 1 */
+		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
+		7000,	/* PowerLimitMinimum */
+		9000,	/* PowerLimitMaximum */
+		28000,	/* TimeWindowMinimum */
+		28000,	/* TimeWindowMaximum */
+		250	/* StepSize */
+	},
+	Package () {	/* Power Limit 2 */
+		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
+		51000,	/* PowerLimitMinimum */
+		51000,	/* PowerLimitMaximum */
+		28000,	/* TimeWindowMinimum */
+		28000,	/* TimeWindowMaximum */
+		1000	/* StepSize */
+	}
+})
diff --git a/src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h b/src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h
new file mode 100644
index 0000000..5b321a3
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_EC_H
+#define VARIANT_EC_H
+
+#include <baseboard/ec.h>
+
+#define EC_ENABLE_MULTIPLE_DPTF_PROFILES
+
+/* Add EC_HOST_EVENT_MKBP from baseboard */
+#undef MAINBOARD_EC_S3_WAKE_EVENTS
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+	(MAINBOARD_EC_S5_WAKE_EVENTS |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)        |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
+/* Removing EC_HOST_EVENT_MKBP from baseboard mask */
+#undef MAINBOARD_EC_SCI_EVENTS
+#define MAINBOARD_EC_SCI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)   |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)  |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)           |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)            |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
+#endif /* VARIANT_EC_H */
diff --git a/src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h b/src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h
new file mode 100644
index 0000000..2193c7b
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+/* Memory configuration board straps */
+#define GPIO_MEM_CONFIG_0	GPP_H19
+#define GPIO_MEM_CONFIG_1	GPP_H22
+#define GPIO_MEM_CONFIG_2	GPP_F10
+#define GPIO_MEM_CONFIG_3	GPP_F3
+
+#endif
diff --git a/src/mainboard/google/hatch/variants/nightfury/memory.c b/src/mainboard/google/hatch/variants/nightfury/memory.c
new file mode 100644
index 0000000..7e1594c
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/nightfury/memory.c
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2020 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <baseboard/gpio.h>
+#include <soc/cnl_memcfg_init.h>
+#include <string.h>
+
+static const struct cnl_mb_cfg baseboard_memcfg = {
+	/*
+	 * The dqs_map arrays map the SoC pins to the lpddr3 pins
+	 * for both channels.
+	 *
+	 * "The index of the array is CPU byte number, the values are DRAM byte
+	 * numbers." - doc #573387
+	 *
+	 * the index = pin number on SoC
+	 * the value = pin number on lpddr3 part
+	 */
+	.dqs_map[DDR_CH0] = {0, 1, 3, 2, 5, 7, 6, 4},
+	.dqs_map[DDR_CH1] = {1, 3, 2, 0, 5, 7, 6, 4},
+
+	.dq_map[DDR_CH0] = {
+		{0xf, 0xf0},
+		{0x0, 0xf0},
+		{0xf, 0xf0},
+		{0xf, 0x0},
+		{0xff, 0x0},
+		{0xff, 0x0}
+	},
+	.dq_map[DDR_CH1] = {
+		{0xf, 0xf0},
+		{0x0, 0xf0},
+		{0xf, 0xf0},
+		{0xf, 0x0},
+		{0xff, 0x0},
+		{0xff, 0x0}
+	},
+
+	/* Nightfury uses 200, 80.6 and 162 rcomp resistors */
+	.rcomp_resistor = {200, 81, 162},
+
+	/* Nightfury Rcomp target values */
+	.rcomp_targets = {100, 40, 40, 23, 40},
+
+	/* Set CaVref config to 0 for LPDDR3 */
+	.vref_ca_config = 0,
+
+	/* Disable Early Command Training */
+	.ect = 0,
+};
+
+void variant_memory_params(struct cnl_mb_cfg *bcfg)
+{
+	memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg));
+}
diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb
new file mode 100644
index 0000000..0cf18e7
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb
@@ -0,0 +1,281 @@
+chip soc/intel/cannonlake
+	register "tdp_pl1_override" = "8"
+	register "tdp_pl2_override" = "51"
+
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci,
+		[PchSerialIoIndexI2C1] = PchSerialIoPci,
+		[PchSerialIoIndexI2C2] = PchSerialIoPci,
+		[PchSerialIoIndexI2C3] = PchSerialIoPci,
+		[PchSerialIoIndexI2C4] = PchSerialIoPci,
+		[PchSerialIoIndexI2C5] = PchSerialIoPci,
+		[PchSerialIoIndexSPI0] = PchSerialIoPci,
+		[PchSerialIoIndexSPI1] = PchSerialIoPci,
+		[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
+	}"
+
+	# No PCIe WiFi
+	register "PcieRpEnable[13]" = "0"
+
+	# Enable DMIC1
+	register "PchHdaAudioLinkDmic1" = "1"
+
+	register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)"        # Type-C Port 0
+	register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)"        # Type-C Port 1
+	register "usb2_ports[2]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[3]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[4]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[5]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)"    # Camera
+	register "usb2_ports[7]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[8]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"     # CnVi BT
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)"     # Type-C Port 0
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)"     # Type-C Port 1
+	register "usb3_ports[2]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[3]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[4]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[5]" = "USB3_PORT_EMPTY"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field	     |	Value			 |
+	#+-------------------+---------------------------+
+	#| I2C0		     | Trackpad			 |
+	#| I2C1		     | Touchscreen		 |
+	#| I2C2		     | Digitizer		 |
+	#| I2C4		     | Audio			 |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 135,
+			.fall_time_ns = 45,
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 60,
+			.fall_time_ns = 25,
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 95,
+			.fall_time_ns = 55,
+		},
+		.i2c[4] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 104,
+			.fall_time_ns = 52,
+		},
+		.gspi[0] = {
+		       .speed_mhz = 1,
+		       .early_init = 1,
+		},
+	}"
+
+	# GPIO for SD card detect
+	register "sdcard_cd_gpio" = "vSD3_CD_B"
+
+	# Enable eMMC HS400
+	register "ScsEmmcHs400Enabled" = "1"
+
+	# EMMC Tx CMD Delay
+	# Refer to EDS-Vol2-14.3.7.
+	# [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
+	# [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
+	register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
+
+	# EMMC TX DATA Delay 1
+	# Refer to EDS-Vol2-14.3.8.
+	# [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
+	# [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
+	register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911"
+
+	# EMMC TX DATA Delay 2
+	# Refer to EDS-Vol2-14.3.9.
+	# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
+	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
+	# [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
+	register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828"
+
+	# EMMC RX CMD/DATA Delay 1
+	# Refer to EDS-Vol2-14.3.10.
+	# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
+	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
+	# [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
+	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b"
+
+	# EMMC RX CMD/DATA Delay 2
+	# Refer to EDS-Vol2-14.3.12.
+	# [17:16] stands for Rx Clock before Output Buffer,
+	#         00: Rx clock after output buffer,
+	#         01: Rx clock before output buffer,
+	#         10: Automatic selection based on working mode.
+	#         11: Reserved
+	# [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
+	# [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
+	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D"
+
+	# EMMC Rx Strobe Delay
+	# Refer to EDS-Vol2-14.3.11.
+	# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
+	# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
+	register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515"
+
+	device domain 0 on
+		device pci 14.0 on
+			chip drivers/usb/acpi
+				device usb 0.0 on
+					chip drivers/usb/acpi
+						register "desc" = ""Left Type-C Port""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device usb 2.0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""Right Type-C Port""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 1)"
+						device usb 2.1 on end
+					end
+					chip drivers/usb/acpi
+						device usb 2.2 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.3 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.4 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.5 off end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device usb 2.6 on end
+					end
+					chip drivers/usb/acpi
+						device usb 2.7 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.8 off end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C14)"
+						device usb 2.9 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""Left Type-C Port""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device usb 3.0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""Right Type-C Port""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(2, 1)"
+						device usb 3.1 on end
+					end
+					chip drivers/usb/acpi
+						device usb 3.2 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.3 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.4 off end
+					end
+				end
+			end
+		end
+
+		device pci 15.0 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.wake" = "GPE0_DW0_21"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 0x20 on end
+			end
+		end # I2C 0
+
+		device pci 15.1 on
+			chip drivers/i2c/generic
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "compat_string" = ""atmel,maxtouch""
+				register "desc" = ""Atmel Touchscreen""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
+				register "reset_delay_ms" = "91" # 90.5 ms
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C12)"
+				register "enable_delay_ms" = "1" # 90 ns
+				register "has_power_resource" = "1"
+				register "disable_gpio_export_in_crs" = "1"
+				register "probed" = "1"
+				device i2c 4b on end
+			end
+
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0001""
+				register "desc" = ""ELAN Touchscreen""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
+				register "probed" = "1"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C12)"
+				register "enable_delay_ms" = "10"
+				register "enable_off_delay_ms" = "100"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
+				register "reset_delay_ms" = "20"
+				register "reset_off_delay_ms" = "2"
+				register "has_power_resource" = "1"
+				device i2c 10 on end
+			end
+		end # I2C #1
+
+		device pci 15.2 off end # I2C #2
+
+		device pci 19.0 on
+			chip drivers/i2c/da7219
+				# TODO: these settings were copied from another board
+				# with the same chip. verify the settings
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
+				register "btn_cfg" = "50"
+				register "mic_det_thr" = "500"
+				register "jack_ins_deb" = "20"
+				register "jack_det_rate" = ""32ms_64ms""
+				register "jack_rem_deb" = "1"
+				register "a_d_btn_thr" = "0xa"
+				register "d_b_btn_thr" = "0x16"
+				register "b_c_btn_thr" = "0x21"
+				register "c_mic_btn_thr" = "0x3e"
+				register "btn_avg" = "4"
+				register "adc_1bit_rpt" = "1"
+				register "micbias_lvl" = "2600"
+				register "mic_amp_in_sel" = ""diff""
+				device i2c 0x1a on end
+			end
+		end
+
+		# No PCIe WiFi
+		device pci 1d.5 off end
+		device pci 1a.0 on  end #eMMC
+		device pci 1e.3 off end # GSPI #1
+		device pci 1f.3 on
+			chip drivers/generic/max98357a
+				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)"
+				register "sdmode_delay" = "5"
+				device generic 0 on end
+			end
+		end # Intel HDA
+	end # domain
+end