commit | f2ee9bc7a30540a1a80c15abd3012dab0b8db0b5 | [log] [tgz] |
---|---|---|
author | Nick Vaccaro <nvaccaro@google.com> | Thu Mar 17 13:06:49 2022 -0700 |
committer | Commit Bot <commit-bot@chromium.org> | Sat Mar 19 07:02:26 2022 +0000 |
tree | 249ca600b4ee217ed2f2e4b243e9e988d1e3d05b | |
parent | b22a12babf084e23b17fac191898f5792eac7a38 [diff] |
UPSTREAM: Revert "Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially"" This reverts a change that was causing hangs and exceptions during boot on an ADL brya4es. The hang (or APIC exception) occurs at what appears to be the FSP MP initialization sequence, prior to the "Display FSP Version Info HOB" log being displayed : [DEBUG] Detected 10 core, 12 thread CPU. [DEBUG] Display FSP Version Info HOB This reverts commit 40ca79714ad7d5f2aa201d83db4d97f21260d924. BUG=b:224873032 TEST=`emerge-brya coreboot chromeos-bootimage`, flash and verify brya4es is able to successfully reboot 200 times without any issues. (cherry picked from commit 1abbb96c36978b5af167c0ed682403a48f32ab05) Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Original-Change-Id: I88c15a51c5d27fbd243478c923e75962d3f8d67d GitOrigin-RevId: 1abbb96c36978b5af167c0ed682403a48f32ab05 Change-Id: I22f6c9885d95fe0c773b3084578747244301b209 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3535013 Tested-by: CopyBot Service Account <copybot.service@gmail.com>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.