commit | b2a72c3d393a227ef082b46dd00539d4cadf3e99 | [log] [tgz] |
---|---|---|
author | Marshall Dawson <marshalldawson3rd@gmail.com> | Fri Oct 12 10:46:17 2018 -0600 |
committer | chrome-bot <chrome-bot@chromium.org> | Sun Oct 14 19:22:00 2018 -0700 |
tree | 2fe0db2b46e5626c6bce99c13dcdbd63b859dd67 | |
parent | a34d22b6e381b23e466ecd7e172b7543653e5391 [diff] |
UPSTREAM: soc/amd/stoneyridge: Define PM USB Enable register Make #define definitions for PMxEF and replace the hardcoded values. Note that this doesn't change the current functionality of the source. The existing code has been propogated from the sb//hudson port, which seems to attempt to enable 100% of all OHCI and EHCI controllers that may be present in the system. BUG=none BRANCH=none TEST=none Change-Id: I39b8c2a3dd4a847c7761bc149b3052fd2092fa2c Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: d453081a57508e25f6d46223e1e8a0f6f93c85ce Original-Change-Id: I6018b0062730de19e3283a010144dfedc2b11423 Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-on: https://review.coreboot.org/29075 Original-Reviewed-by: Martin Roth <martinroth@google.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/1280009 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.