commit | 6558fcf310ca492dd07efe51fa28694a8d7d2353 | [log] [tgz] |
---|---|---|
author | Puthikorn Voravootivat <puthik@google.com> | Wed Jun 10 15:17:58 2020 -0700 |
committer | Commit Bot <commit-bot@chromium.org> | Wed Jun 17 14:05:49 2020 +0000 |
tree | 76ec268bb8429366464f49a4b4c9b8f43ca329f0 | |
parent | 09a9235eb7dfe27c6c2079a243400ffa8ea72526 [diff] |
UPSTREAM: mb/google/hatch: mushu: Add F75303 temp sensor to dptf Update the following in dptf.asl - Add support for TSR3 - Change TSR0/TSR1/TSR2/TSR3 From: Charger, 5V, GPU , None To: Charger, GPU, F75303_GPU, F75303_GPU_POWER - Adjust fan/cpu trip point accordingly - Fix formating in dptf.asl - Throttle charger when TSR0 (charger) is hot instead of throttle CPU BUG=b:158676970 BRANCH=None TEST=grep . /sys/class/thermal/thermal_zone5/{type,temp} /sys/class/thermal/thermal_zone5/type:TSR3 /sys/class/thermal/thermal_zone5/temp:50800 Change-Id: I7e35606cf90bbb1156b941029f4a914a8572c0a7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 549a853f8f50cb99098f7abec6e93efe7224ee82 Original-Change-Id: Iedbb6bc7c1e59a027119c70791b9bc8a4d83ff87 Original-Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/42270 Original-Reviewed-by: Shelley Chen <shchen@google.com> Original-Reviewed-by: Bob Moragues <moragues@chromium.org> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2248114 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Commit-Queue: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.