| commit | a1271a2b2916969fe3b3a7b8893372bdd246ac94 | [log] [tgz] |
|---|---|---|
| author | zhaojohn <john.zhao@intel.com> | Tue Oct 25 12:38:20 2022 -0700 |
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | Thu Nov 03 05:19:10 2022 +0000 |
| tree | a8d9c3fda568a1b9e0bfdf6b54120140341f57ae | |
| parent | ed784e0d8dddcd015e0b9394cbfafee449a8c780 [diff] |
UPSTREAM: mb/google/rex: Disable TBT PCIe rp1 and rp3 root ports Rex board only uses TBT PCIe root ports 0 and 2. This change disables rp1 and rp3 root ports. BUG=b:254207628 TEST=Booted to OS and verified rp1 and rp3 root ports were disabled. (cherry picked from commit 80a3b9659325bbefa9403f96ecae9303df347b79) Original-Change-Id: Ia5c1d657c0ad0482619d739f8949bc9168eac25b Original-Signed-off-by: zhaojohn <john.zhao@intel.com> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/68854 Original-Reviewed-by: Subrata Banik <subratabanik@google.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Tarun Tuli <taruntuli@google.com> Original-Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Original-Reviewed-by: Kapil Porwal <kapilporwal@google.com> GitOrigin-RevId: 80a3b9659325bbefa9403f96ecae9303df347b79 Change-Id: I1aacbddb089d751d3d1a4a82808f1c96cfd31c83 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3999241 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@chromium.org> Commit-Queue: Kangheui Won <khwon@chromium.org> Tested-by: CopyBot Service Account <copybot.service@gmail.com>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig and make nconfig)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.