| /* $NoKeywords:$ */ |
| /** |
| * @file |
| * |
| * PCIe port initialization service procedure |
| * |
| * |
| * |
| * @xrefitem bom "File Content Label" "Release Content" |
| * @e project: AGESA |
| * @e sub-project: GNB |
| * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| * |
| */ |
| /* |
| ***************************************************************************** |
| * |
| * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. |
| * |
| * AMD is granting you permission to use this software (the Materials) |
| * pursuant to the terms and conditions of your Software License Agreement |
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| * of these Materials shall constitute your acceptance of those terms and |
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| * License Agreement, please do not use any portion of these Materials. |
| * |
| * CONFIDENTIALITY: The Materials and all other information, identified as |
| * confidential and provided to you by AMD shall be kept confidential in |
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| * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION |
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| * *************************************************************************** |
| * |
| */ |
| |
| /*---------------------------------------------------------------------------------------- |
| * M O D U L E S U S E D |
| *---------------------------------------------------------------------------------------- |
| */ |
| #include "AGESA.h" |
| #include "Ids.h" |
| #include "amdlib.h" |
| #include "Gnb.h" |
| #include "GnbPcieConfig.h" |
| #include "GnbCommonLib.h" |
| #include "GnbPcieInitLibV1.h" |
| #include "PciePortServicesV4.h" |
| #include "GnbRegistersTN.h" |
| #include "Filecode.h" |
| #define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPORTSERVICESV4_FILECODE |
| /*---------------------------------------------------------------------------------------- |
| * D E F I N I T I O N S A N D M A C R O S |
| *---------------------------------------------------------------------------------------- |
| */ |
| |
| |
| /*---------------------------------------------------------------------------------------- |
| * T Y P E D E F S A N D S T R U C T U R E S |
| *---------------------------------------------------------------------------------------- |
| */ |
| |
| |
| /*---------------------------------------------------------------------------------------- |
| * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| *---------------------------------------------------------------------------------------- |
| */ |
| |
| |
| /*----------------------------------------------------------------------------------------*/ |
| /** |
| * Set current link speed |
| * |
| * |
| * @param[in] LinkSpeedCapability Link Speed Capability |
| * @param[in] Engine Pointer to engine configuration descriptor |
| * @param[in] Pcie Pointer to global PCIe configuration |
| * |
| */ |
| VOID |
| PcieSetLinkSpeedCapV4 ( |
| IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, |
| IN PCIe_ENGINE_CONFIG *Engine, |
| IN PCIe_PLATFORM_CONFIG *Pcie |
| ) |
| { |
| DxF0xE4_xA4_STRUCT DxF0xE4_xA4; |
| DxF0xE4_xC0_STRUCT DxF0xE4_xC0; |
| DxF0x88_STRUCT DxF0x88; |
| GnbLibPciRead ( |
| Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS, |
| AccessWidth32, |
| &DxF0x88.Value, |
| GnbLibGetHeader (Pcie) |
| ); |
| DxF0xE4_xA4.Value = PciePortRegisterRead ( |
| Engine, |
| DxF0xE4_xA4_ADDRESS, |
| Pcie |
| ); |
| DxF0xE4_xC0.Value = PciePortRegisterRead ( |
| Engine, |
| DxF0xE4_xC0_ADDRESS, |
| Pcie |
| ); |
| |
| switch (LinkSpeedCapability) { |
| case PcieGen2: |
| DxF0xE4_xA4.Field.LcGen2EnStrap = 0x1; |
| DxF0xE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x1; |
| DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x0; |
| DxF0x88.Field.TargetLinkSpeed = 0x2; |
| DxF0x88.Field.HwAutonomousSpeedDisable = 0x0; |
| break; |
| case PcieGen1: |
| DxF0xE4_xA4.Field.LcGen2EnStrap = 0x0; |
| DxF0xE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x0; |
| DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x1; |
| DxF0x88.Field.TargetLinkSpeed = 0x1; |
| DxF0x88.Field.HwAutonomousSpeedDisable = 0x1; |
| PcieRegisterWriteField ( |
| PcieConfigGetParentWrapper (Engine), |
| WRAP_SPACE (PcieConfigGetParentWrapper (Engine)->WrapId, D0F0xE4_WRAP_0803_ADDRESS + 0x100 * Engine->Type.Port.PortId), |
| D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET, |
| D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH, |
| 0, |
| FALSE, |
| Pcie |
| ); |
| break; |
| default: |
| ASSERT (FALSE); |
| break; |
| } |
| PciePortRegisterWrite ( |
| Engine, |
| DxF0xE4_xA4_ADDRESS, |
| DxF0xE4_xA4.Value, |
| FALSE, |
| Pcie |
| ); |
| PciePortRegisterWrite ( |
| Engine, |
| DxF0xE4_xC0_ADDRESS, |
| DxF0xE4_xC0.Value, |
| FALSE, |
| Pcie |
| ); |
| GnbLibPciWrite ( |
| Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS, |
| AccessWidth32, |
| &DxF0x88.Value, |
| GnbLibGetHeader (Pcie) |
| ); |
| } |
| /*----------------------------------------------------------------------------------------*/ |
| /** |
| * Enable passing TLP prefix to IOMMU if IOMMU enabled |
| * |
| * |
| * @param[in] Engine Pointer to engine configuration descriptor |
| * @param[in] Pcie Pointer to global PCIe configuration |
| * |
| */ |
| VOID |
| PcieInitPortForIommuV4 ( |
| IN PCIe_ENGINE_CONFIG *Engine, |
| IN PCIe_PLATFORM_CONFIG *Pcie |
| ) |
| { |
| PciePortRegisterRMW ( |
| Engine, |
| DxF0xE4_xC1_ADDRESS, |
| DxF0xE4_xC1_StrapE2EPrefixEn_MASK | DxF0xE4_xC1_StrapExtendedFmtSupported_MASK, |
| (1 << DxF0xE4_xC1_StrapE2EPrefixEn_OFFSET) | (1 << DxF0xE4_xC1_StrapExtendedFmtSupported_OFFSET), |
| TRUE, |
| Pcie |
| ); |
| } |
