| /* $NoKeywords:$ */ |
| /** |
| * @file |
| * |
| * Config FCH USB OHCI controller |
| * |
| * Init USB OHCI features. |
| * |
| * @xrefitem bom "File Content Label" "Release Content" |
| * @e project: AGESA |
| * @e sub-project: FCH |
| * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| * |
| */ |
| /*;******************************************************************************** |
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| #include "FchPlatform.h" |
| #include "Filecode.h" |
| #define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCIENVSERVICE_FILECODE |
| // |
| // Declaration of local functions |
| // |
| // |
| // Declaration of local functions |
| // |
| /** |
| * FchSetUsbEnableReg |
| * emulation |
| * |
| * |
| * |
| * @param[in] FchDataPtr Fch configuration structure pointer. |
| * |
| */ |
| VOID |
| FchSetUsbEnableReg ( |
| IN FCH_DATA_BLOCK *FchDataPtr |
| ) |
| { |
| UINT8 UsbModeReg; |
| UINT8 XhciReg00; |
| UsbModeReg = 0; |
| |
| // Overwrite EHCI3/OHCI3 by Xhci1Enable |
| ReadMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth8, &XhciReg00); |
| if (XhciReg00 & BIT0) { |
| FchDataPtr->Usb.Ohci3Enable = FALSE; |
| FchDataPtr->Usb.Ehci3Enable = FALSE; |
| UsbModeReg |= 0x80; |
| } else { |
| UsbModeReg &= 0x7F; |
| } |
| |
| if ( FchDataPtr->Usb.Ohci1Enable ) { |
| UsbModeReg |= 0x01; |
| } |
| if ( FchDataPtr->Usb.Ehci1Enable ) { |
| UsbModeReg |= 0x02; |
| } |
| if ( FchDataPtr->Usb.Ohci2Enable ) { |
| UsbModeReg |= 0x04; |
| } |
| if ( FchDataPtr->Usb.Ehci2Enable ) { |
| UsbModeReg |= 0x08; |
| } |
| if ( FchDataPtr->Usb.Ohci3Enable ) { |
| UsbModeReg |= 0x10; |
| } |
| if ( FchDataPtr->Usb.Ehci3Enable ) { |
| UsbModeReg |= 0x20; |
| } |
| if ( FchDataPtr->Usb.Ohci4Enable ) { |
| UsbModeReg |= 0x40; |
| } |
| |
| RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xEF , AccessWidth8, 0, UsbModeReg); |
| } |
| |