| /* $NoKeywords:$ */ |
| /** |
| * @file |
| * |
| * Config Fch LPC controller |
| * |
| * Init LPC Controller features. |
| * |
| * @xrefitem bom "File Content Label" "Release Content" |
| * @e project: AGESA |
| * @e sub-project: FCH |
| * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| * |
| */ |
| /* |
| ***************************************************************************** |
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| */ |
| #include "FchPlatform.h" |
| #include "Filecode.h" |
| #define FILECODE PROC_FCH_SPI_FAMILY_HUDSON2_HUDSON2LPCENVSERVICE_FILECODE |
| |
| /** |
| * FchInitHudson2EnvLpcPciTable - PCI device registers initial |
| * during early POST. |
| * |
| */ |
| REG8_MASK FchInitHudson2EnvLpcPciTable[] = |
| { |
| // |
| // LPC Device (Bus 0, Dev 20, Func 3) |
| // |
| {0x00, LPC_BUS_DEV_FUN, 0}, |
| {FCH_LPC_REG40, (UINT8)~BIT2, BIT2}, /// Enabling LPC DMA Function 0x40[2]=1b 0x78[0]=0b |
| {FCH_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2}, |
| {0x78 , 0xFC, 00}, /// Enabling LPC DMA Function 0x40[2]=1b 0x78[0]=0b / Disables MSI capability |
| {FCH_LPC_REGBB, (UINT8)~BIT0, (BIT0 + BIT3 + BIT4 + BIT5)}, /// Enabled SPI Prefetch from HOST. |
| {0xFF, 0xFF, 0xFF}, |
| }; |
| |
| /** |
| * FchInitEnvLpcProgram - Config LPC controller before PCI |
| * emulation |
| * |
| * |
| * |
| * @param[in] FchDataPtr Fch configuration structure pointer. |
| * |
| */ |
| VOID |
| FchInitEnvLpcProgram ( |
| IN VOID *FchDataPtr |
| ) |
| { |
| FCH_DATA_BLOCK *LocalCfgPtr; |
| AMD_CONFIG_PARAMS *StdHeader; |
| LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; |
| StdHeader = LocalCfgPtr->StdHeader; |
| |
| ProgramPciByteTable ((REG8_MASK*) (&FchInitHudson2EnvLpcPciTable[0]), sizeof (FchInitHudson2EnvLpcPciTable) / sizeof (REG8_MASK), StdHeader); |
| |
| // |
| // Disable LPC A-Link Cycle Bypass |
| // |
| RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG50 + 2, AccessWidth8, 0xF7, BIT3); |
| } |
| |