| /* $NoKeywords:$ */ |
| /** |
| * @file |
| * |
| * Config Fch Gpp controller |
| * |
| * Init Gpp features (PEI phase). |
| * |
| * @xrefitem bom "File Content Label" "Release Content" |
| * @e project: AGESA |
| * @e sub-project: FCH |
| * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| * |
| */ |
| /* |
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| */ |
| #include "FchPlatform.h" |
| #include "Filecode.h" |
| #define FILECODE PROC_FCH_PCIE_GPPRESET_FILECODE |
| |
| |
| // |
| //----------------------------------------------------------------------------------- |
| // Early GPP initialization sequence: |
| // |
| // 1) Set port enable bit fields by current GPP link configuration mode |
| // 2) Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0) |
| // 3) Loop polling for the link status of all ports |
| // 4) Misc operations after link training: |
| // - (optional) Detect GFX device |
| // - Hide empty GPP configuration spaces (Disable empty GPP ports) |
| // - (optional) Power down unused GPP ports |
| // - (optional) Configure PCIE_P2P_Int_Map (abcfg:0xC4[7:0]) |
| // 5) GPP init completed |
| // |
| // |
| // *) Gen2 vs Gen1 |
| // Gen2 mode Gen1 mode |
| // --------------------------------------------------------------- |
| // STRAP_PHY_PLL_CLKF[6:0] 7'h32 7'h19 |
| // STRAP_BIF_GEN2_EN 1 0 |
| // |
| // PCIE_PHY_PLL clock locks @ 5GHz |
| // |
| // |
| |
| /** |
| * FchInitResetGpp - Config Gpp during Power-On |
| * |
| * |
| * |
| * @param[in] FchDataPtr Fch configuration structure pointer. |
| * |
| */ |
| VOID |
| FchInitResetGpp ( |
| IN VOID *FchDataPtr |
| ) |
| { |
| FCH_RESET_DATA_BLOCK *LocalCfgPtr; |
| AMD_CONFIG_PARAMS *StdHeader; |
| |
| LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr; |
| StdHeader = LocalCfgPtr->StdHeader; |
| if ( LocalCfgPtr->Gpp.NewGppAlgorithm == TRUE ) { |
| if (ReadFchSleepType (StdHeader) == ACPI_SLPTYP_S3) { |
| FchGppPortInitS3Phase (&LocalCfgPtr->Gpp, StdHeader); |
| } |
| } |
| } |
| |
| |