| /* $NoKeywords:$ */ |
| /** |
| * @file |
| * |
| * Config Hudson2 Pcie controller |
| * |
| * Init GPP (pcie Controller) features. |
| * |
| * @xrefitem bom "File Content Label" "Release Content" |
| * @e project: AGESA |
| * @e sub-project: FCH |
| * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| * |
| */ |
| /* |
| ***************************************************************************** |
| * |
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| **************************************************************************** |
| */ |
| #include "FchPlatform.h" |
| #include "Ids.h" |
| #include "Filecode.h" |
| #define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPSERVICE_FILECODE |
| |
| /** |
| * ProgramGppTogglePcieReset - Toggle PCIE_RST2# |
| * |
| * |
| * @param[in] DoToggling |
| * @param[in] StdHeader |
| * |
| */ |
| VOID |
| ProgramGppTogglePcieReset ( |
| IN BOOLEAN DoToggling, |
| IN AMD_CONFIG_PARAMS *StdHeader |
| ) |
| { |
| if (DoToggling) { |
| FchResetPcie (FchBlock, AssertReset, StdHeader); |
| FchStall (500, StdHeader); |
| FchResetPcie (FchBlock, DeassertReset, StdHeader); |
| } else { |
| RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GEVENT_REG04, AccessWidth8, (UINT32)~(BIT1 + BIT0), 0x02); |
| } |
| } |
| |
| /** |
| * FchGppDynamicPowerSaving - GPP Dynamic Power Saving |
| * |
| * |
| * @param[in] FchGpp Pointer to Fch GPP configuration structure |
| * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS |
| * |
| */ |
| VOID |
| FchGppDynamicPowerSaving ( |
| IN FCH_GPP *FchGpp, |
| IN AMD_CONFIG_PARAMS *StdHeader |
| ) |
| { |
| FCH_GPP_PORT_CONFIG *PortCfg; |
| UINT32 GppData32; |
| UINT32 HoldGppData32; |
| UINT32 AbValue; |
| |
| if (!FchGpp->GppDynamicPowerSaving || FchGpp->SerialDebugBusEnable) { |
| return; |
| } |
| |
| if (FchGpp->GppHardwareDownGrade) { |
| PortCfg = &FchGpp->PortCfg[FchGpp->GppHardwareDownGrade - 1]; |
| PortCfg->PortDetected = TRUE; |
| } |
| |
| GppData32 = 0; |
| HoldGppData32 = 0; |
| |
| switch ( FchGpp->GppLinkConfig ) { |
| case PortA4: |
| PortCfg = &FchGpp->PortCfg[0]; |
| if ( PortCfg->PortDetected == FALSE ) { |
| GppData32 |= 0x0f0f; |
| HoldGppData32 |= 0x1000; |
| } |
| break; |
| |
| case PortA2B2: |
| PortCfg = &FchGpp->PortCfg[0]; |
| if ( PortCfg->PortDetected == FALSE ) { |
| GppData32 |= ( FchGpp->GppLaneReversal )? 0x0c0c:0x0303; |
| HoldGppData32 |= 0x1000; |
| } |
| |
| PortCfg = &FchGpp->PortCfg[1]; |
| if ( PortCfg->PortDetected == FALSE ) { |
| GppData32 |= ( FchGpp->GppLaneReversal )? 0x0303:0x0c0c; |
| HoldGppData32 |= 0x2000; |
| } |
| break; |
| |
| case PortA2B1C1: |
| PortCfg = &FchGpp->PortCfg[0]; |
| if ( PortCfg->PortDetected == FALSE ) { |
| GppData32 |= ( FchGpp->GppLaneReversal )? 0x0c0c:0x0303; |
| HoldGppData32 |= 0x1000; |
| } |
| |
| PortCfg = &FchGpp->PortCfg[1]; |
| if ( PortCfg->PortDetected == FALSE ) { |
| GppData32 |= ( FchGpp->GppLaneReversal )? 0x0202:0x0404; |
| HoldGppData32 |= 0x2000; |
| } |
| |
| PortCfg = &FchGpp->PortCfg[2]; |
| if ( PortCfg->PortDetected == FALSE ) { |
| GppData32 |= ( FchGpp->GppLaneReversal )? 0x0101:0x0808; |
| HoldGppData32 |= 0x4000; |
| } |
| break; |
| |
| case PortA1B1C1D1: |
| PortCfg = &FchGpp->PortCfg[0]; |
| if ( PortCfg->PortDetected == FALSE ) { |
| GppData32 |= ( FchGpp->GppLaneReversal )? 0x0808:0x0101; |
| HoldGppData32 |= 0x1000; |
| } |
| |
| PortCfg = &FchGpp->PortCfg[1]; |
| if ( PortCfg->PortDetected == FALSE ) { |
| GppData32 |= ( FchGpp->GppLaneReversal )? 0x0404:0x0202; |
| HoldGppData32 |= 0x2000; |
| } |
| |
| PortCfg = &FchGpp->PortCfg[2]; |
| if ( PortCfg->PortDetected == FALSE ) { |
| GppData32 |= ( FchGpp->GppLaneReversal )? 0x0202:0x0404; |
| HoldGppData32 |= 0x4000; |
| } |
| |
| PortCfg = &FchGpp->PortCfg[3]; |
| if ( PortCfg->PortDetected == FALSE ) { |
| GppData32 |= ( FchGpp->GppLaneReversal )? 0x0101:0x0808; |
| HoldGppData32 |= 0x8000; |
| } |
| break; |
| |
| default: |
| ASSERT (FALSE); |
| break; |
| } |
| |
| // |
| // Power Saving With GPP Disable |
| // ABCFG 0xC0[8] = 0x0 |
| // ABCFG 0xC0[15:12] = 0xF |
| // Enable "Power Saving Feature for A-Link Express Lanes" |
| // Enable "Power Saving Feature for GPP Lanes" |
| // ABCFG 0x90[19] = 1 |
| // ABCFG 0x90[6] = 1 |
| // RCINDC_Reg 0x65 [27:0] = 0xFFFFFFF |
| // ABCFG 0xC0[7:4] = 0x0 |
| // |
| if (FchGpp->UmiPhyPllPowerDown && FchGpp->GppPhyPllPowerDown ) { |
| AbValue = ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader); |
| WriteAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), (( AbValue | HoldGppData32 ) & (~ BIT8 )), StdHeader); |
| RwAlink (FCH_AX_INDXC_REG40, (UINT32)~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12), StdHeader); |
| RwAlink ((FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29)), 0xFFFFFFFF, (BIT6 + BIT19), StdHeader); |
| RwAlink (FCH_RCINDXC_REG65, 0xFFFFFFFF, ((GppData32 & 0x0F) == 0x0F) ? GppData32 | 0x0CFF0000 : GppData32, StdHeader); |
| } |
| } |
| |