| /* $NoKeywords:$ */ |
| /** |
| * @file |
| * |
| * Config Fch Pcib controller |
| * |
| * Init Pcib Controller features (PEI phase). |
| * |
| * @xrefitem bom "File Content Label" "Release Content" |
| * @e project: AGESA |
| * @e sub-project: FCH |
| * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| * |
| */ |
| /* |
| ***************************************************************************** |
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| **************************************************************************** |
| */ |
| #include "FchPlatform.h" |
| #define FILECODE PROC_FCH_PCIB_PCIBRESET_FILECODE |
| /** |
| * FchInitResetPcibPciTable - Pcib device registers initial |
| * during the power on stage. |
| * |
| * |
| * |
| * |
| */ |
| REG8_MASK FchInitResetPcibPciTable[] = |
| { |
| // |
| // P2P Bridge (Bus 0, Dev 20, Func 4) |
| // |
| {0x00, PCIB_BUS_DEV_FUN, 0}, |
| {FCH_PCIB_REG4B, 0xFF, BIT6 + BIT7 + BIT4}, |
| {FCH_PCIB_REG40, 0xDF, 0x20}, |
| {0x50 , 0x02, 0x01}, |
| {0xFF, 0xFF, 0xFF}, |
| }; |
| |
| /** |
| * FchInitResetPcib - Config Pcib controller during Power-On |
| * |
| * |
| * |
| * @param[in] FchDataPtr Fch configuration structure pointer. |
| * |
| */ |
| VOID |
| FchInitResetPcib ( |
| IN VOID *FchDataPtr |
| ) |
| { |
| AMD_CONFIG_PARAMS *StdHeader; |
| |
| StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader; |
| |
| ProgramPciByteTable ( |
| (REG8_MASK*) (&FchInitResetPcibPciTable[0]), |
| sizeof (FchInitResetPcibPciTable) / sizeof (REG8_MASK), |
| StdHeader |
| ); |
| if ( UserOptions.FchBldCfg->CfgFchPort80BehindPcib ) { |
| FchInitResetPcibPort80Enable (FchDataPtr); |
| } |
| } |
| |
| /** |
| * FchInitResetPcibPort80Enable - Pcib device registers initial |
| * during the power on stage. |
| * |
| * |
| * |
| * |
| */ |
| REG8_MASK FchInitResetPcibPort80EnableTable[] = |
| { |
| // |
| // P2P Bridge (Bus 0, Dev 20, Func 4) |
| // |
| {0x00, PCIB_BUS_DEV_FUN, 0}, |
| {0x1C , 0x00, 0xF0}, |
| {0x1D , 0x00, 0x00}, |
| {0x04 , 0x00, 0x21}, |
| {0xFF, 0xFF, 0xFF}, |
| }; |
| |
| /** |
| * FchInitResetPcibPort80Enable - Enable Port80 Behind PCIB |
| * |
| * |
| * |
| * @param[in] FchDataPtr Fch configuration structure pointer. |
| * |
| */ |
| VOID |
| FchInitResetPcibPort80Enable ( |
| IN VOID *FchDataPtr |
| ) |
| { |
| AMD_CONFIG_PARAMS *StdHeader; |
| |
| StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader; |
| |
| ProgramPciByteTable ( |
| (REG8_MASK*) (&FchInitResetPcibPort80EnableTable[0]), |
| sizeof (FchInitResetPcibPort80EnableTable) / sizeof (REG8_MASK), |
| StdHeader |
| ); |
| } |
| |