src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibEnv.c

/* $NoKeywords:$ */
/**
 * @file
 *
 * Config Fch Pcib controller
 *
 * Init Pcib Controller features.
 *
 * @xrefitem bom "File Content Label" "Release Content"
 * @e project:     AGESA
 * @e sub-project: FCH
 * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
 *
 */
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#include "FchPlatform.h"
#define FILECODE PROC_FCH_PCIB_PCIBENV_FILECODE

/**
 * FchInitEnvPcibPciTable - PCI device registers initial during
 * early POST.
 *
 */
REG8_MASK FchInitEnvPcibPciTable[] =
{
  //
  // PCIB Bridge (Bus 0, Dev 20, Func 4)
  //
  {0x00, PCIB_BUS_DEV_FUN, 0},
  {FCH_PCIB_REG40, 0xFF, BIT5},      /// PCI-bridge Subtractive Decode
  {FCH_PCIB_REG4B, 0xFF, BIT7},      ///
  {0x66 , 0xFF, BIT4},      /// Enabling One-Prefetch-Channel Mode, PCIB_PCI_config 0x64 [20]
  {0x65 , 0xFF, BIT7},      /// proper operation of CLKRUN#.
  {FCH_PCIB_REG0D, 0x00, 0x40},      /// Setting Latency Timers to 0x40, Enables the PCIB to retain ownership
  {FCH_PCIB_REG1B, 0x00, 0x40},      /// of the bus on the Primary side and on the Secondary side when GNT# is deasserted.
  {FCH_PCIB_REG66 + 1, 0xFF, BIT1},  /// Enable PCI bus GNT3#..
  {0xFF, 0xFF, 0xFF},
};

/**
 * FchInitEnvPcib - Config Pcib controller before PCI emulation
 *
 *
 *
 * @param[in] FchDataPtr Fch configuration structure pointer.
 *
 */
VOID
FchInitEnvPcib (
  IN  VOID     *FchDataPtr
  )
{
  UINT8        VerbPciClks;
  FCH_DATA_BLOCK         *LocalCfgPtr;
  AMD_CONFIG_PARAMS      *StdHeader;

  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
  StdHeader = LocalCfgPtr->StdHeader;

  //
  //Early post initialization of pci config space
  //
  ProgramPciByteTable ((REG8_MASK*) (&FchInitEnvPcibPciTable[0]), sizeof (FchInitEnvPcibPciTable) / sizeof (REG8_MASK), StdHeader);

  //
  //Disable or Enable PCI Clks based on input
  //
  VerbPciClks = ((LocalCfgPtr->Pcib.PciClks & 0x0F) << 2);
  RwPci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG42, AccessWidth8, (UINT32)~(BIT5 + BIT4 + BIT3 + BIT2), VerbPciClks, StdHeader);
  VerbPciClks = ((LocalCfgPtr->Pcib.PciClks & 0x10) >> 4);
  RwPci ((PCIB_BUS_DEV_FUN << 16) + 0x4A , AccessWidth8, (UINT32)~BIT0, VerbPciClks, StdHeader);
  //
  // PCIB MSI
  //
  if (LocalCfgPtr->Pcib.PcibMsiEnable) {
    RwPci ((PCIB_BUS_DEV_FUN << 16) + 0x40 , AccessWidth8, (UINT32)~BIT3, BIT3, StdHeader);
  }
}