src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcReset.c

/* $NoKeywords:$ */
/**
 * @file
 *
 * Config Fch Ec controller
 *
 * Init Ec Controller features (PEI phase).
 *
 * @xrefitem bom "File Content Label" "Release Content"
 * @e project:     AGESA
 * @e sub-project: FCH
 * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
 *
 */
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*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_IMC_FCHECRESET_FILECODE

/**
 * FchInitResetEc - Config Ec controller during Power-On
 *
 *
 *
 * @param[in] FchDataPtr Fch configuration structure pointer.
 *
 */
VOID
FchInitResetEc (
  IN  VOID     *FchDataPtr
  )
{
  FCH_RESET_DATA_BLOCK      *LocalCfgPtr;
  AMD_CONFIG_PARAMS         *StdHeader;

  LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
  StdHeader = LocalCfgPtr->StdHeader;

  //
  //Enable config mode
  //
  EnterEcConfig (StdHeader);

  //
  //Do settings for mailbox - logical device 0x09
  //
  RwEc8 (0x07, 0x00, 0x09, StdHeader);                      ///switch to device 9 (Mailbox)
  RwEc8 (0x60, 0x00, (MailBoxPort >> 8), StdHeader);        ///set MSB of Mailbox port
  RwEc8 (0x61, 0x00, (MailBoxPort & 0xFF), StdHeader);      ///set LSB of Mailbox port
  RwEc8 (0x30, 0x00, 0x01, StdHeader);                      ///;Enable Mailbox Registers Interface, bit0=1

  if ( LocalCfgPtr->EcKbd == ENABLED) {
    //
    //Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC
    //
    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD6, AccessWidth8, (UINT32)~BIT8, BIT0 + BIT1 + BIT2 + BIT3);

    //
    //Disable LPC Decoding of port 60/64
    //
    RwPci (((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG47), AccessWidth8, (UINT32)~BIT5, 0, StdHeader);

    //
    //Enable logical device 0x07 (Keyboard controller)
    //
    RwEc8 (0x07, 0x00, 0x07, StdHeader);
    RwEc8 (0x30, 0x00, 0x01, StdHeader);
  }

  if (IsImcEnabled (StdHeader) && ( LocalCfgPtr->EcChannel0 == ENABLED)) {
    //
    //Logical device 0x03
    //
    RwEc8 (0x07, 0x00, 0x03, StdHeader);
    RwEc8 (0x60, 0x00, 0x00, StdHeader);
    RwEc8 (0x61, 0x00, 0x62, StdHeader);
    RwEc8 (0x30, 0x00, 0x01, StdHeader);                    ///;Enable Device 3
  }

  //
  //Enable EC (IMC) to generate SMI to BIOS
  //
  RwMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB3, AccessWidth8, (UINT32)~BIT6, BIT6);
  ExitEcConfig (StdHeader);
}