src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeEnv.c

/* $NoKeywords:$ */
/**
 * @file
 *
 * Config Fch IDE controller
 *
 * Init IDE Controller features.
 *
 * @xrefitem bom "File Content Label" "Release Content"
 * @e project:     AGESA
 * @e sub-project: FCH
 * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
 *
 */
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*/
#include "FchPlatform.h"
#define FILECODE PROC_FCH_IDE_IDEENV_FILECODE

/**
 * FchInitEnvIde - Config Ide controller before PCI emulation
 *
 *
 *
 * @param[in] FchDataPtr Fch configuration structure pointer.
 *
 */
VOID
FchInitEnvIde (
  IN  VOID     *FchDataPtr
  )
{
  UINT8        Channel;
  FCH_DATA_BLOCK         *LocalCfgPtr;
  AMD_CONFIG_PARAMS      *StdHeader;

  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
  StdHeader = LocalCfgPtr->StdHeader;

  RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG40), AccessWidth8, 0xff, BIT0, StdHeader);

  //
  // Enabling IDE Explicit Pre-Fetch  IDE PCI Config 0x62[8]=0
  //
  RwPci (((IDE_BUS_DEV_FUN << 16) + 0x62  + 1), AccessWidth8,  (UINT32)~BIT0, BIT5, StdHeader);

  //
  // Disable SATA MSI
  //
  RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG34), AccessWidth8, 0x00, 0x00, StdHeader);
  RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG06), AccessWidth8, 0xEF, 0x00, StdHeader);

  //
  // Set Ide Channel enable/disable by parameter
  //
  ReadPci (((IDE_BUS_DEV_FUN << 16) + 0x040  + 11), AccessWidth8, &Channel, StdHeader);
  Channel &= 0xCF;
  if ( LocalCfgPtr->Sata.IdeDisUnusedIdePChannel ) {
    Channel |= 0x10;
  }
  if ( LocalCfgPtr->Sata.IdeDisUnusedIdeSChannel ) {
    Channel |= 0x20;
  }
  WritePci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG40 + 11), AccessWidth8, &Channel, StdHeader);

  //
  // IDE Controller Class ID & SSID
  // ** Get Sata Configuration ** for sync Sata & Ide with only one Legacy Ide device
  //
  if ( (LocalCfgPtr->Sata.SataIdeMode == 1) && (LocalCfgPtr->Sata.SataClass != SataLegacyIde) ) {
    //
    // Write the class code to IDE PCI register 08h-0Bh
    //
    RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG08), AccessWidth32, 0, 0x01018F40, StdHeader);
  }
  if ( LocalCfgPtr->Sata.SataClass == SataLegacyIde ) {
    //
    //Set SATA controller to native mode
    //
    RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG09), AccessWidth8, 0x00, 0x08F, StdHeader);
  }
  if (LocalCfgPtr->Ide.IdeSsid != 0 ) {
    RwPci ((IDE_BUS_DEV_FUN << 16) + 0x2C , AccessWidth32, 0x00, LocalCfgPtr->Ide.IdeSsid, StdHeader);
  }

  //
  // Disable write access to PCI header
  //
  RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG40), AccessWidth8, (UINT32)~BIT0, 0, StdHeader);
}