| /* $NoKeywords:$ */ |
| /** |
| * @file |
| * |
| * AMD Family_15 MMIO map manager |
| * |
| * manage MMIO base/limit registers. |
| * |
| * @xrefitem bom "File Content Label" "Release Content" |
| * @e project: AGESA |
| * @e sub-project: CPU/Family/0x15 |
| * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| * |
| */ |
| /* |
| ****************************************************************************** |
| * |
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| * |
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| ****************************************************************************** |
| */ |
| |
| #ifndef _CPU_F15_MMIO_MAP_H_ |
| #define _CPU_F15_MMIO_MAP_H_ |
| |
| |
| /*--------------------------------------------------------------------------------------- |
| * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) |
| *--------------------------------------------------------------------------------------- |
| */ |
| |
| |
| /*--------------------------------------------------------------------------------------- |
| * D E F I N I T I O N S A N D M A C R O S |
| *--------------------------------------------------------------------------------------- |
| */ |
| #define MMIO_REG_PAIR_NUM 12 |
| |
| #define CONF_MAP_RANGE_0 0xE0 |
| #define CONF_MAP_RANGE_1 0xE4 |
| #define CONF_MAP_RANGE_2 0xE8 |
| #define CONF_MAP_RANGE_3 0xEC |
| #define CONF_MAP_NUM 4 |
| /*--------------------------------------------------------------------------------------- |
| * T Y P E D E F S, S T R U C T U R E S, E N U M S |
| *--------------------------------------------------------------------------------------- |
| */ |
| /// MMIO base low |
| typedef struct { |
| UINT32 RE:1; ///< Read enable |
| UINT32 WE:1; ///< Write enable |
| UINT32 CpuDis:1; ///< CPU Disable |
| UINT32 Lock:1; ///< Lock |
| UINT32 :4; ///< Reserved |
| UINT32 MmioBase:24; ///< MMIO base address register bits[39:16] |
| } MMIO_BASE_LOW; |
| |
| /// MMIO limit low |
| typedef struct { |
| UINT32 DstNode:3; ///< Destination node ID bits |
| UINT32 :1; ///< Reserved |
| UINT32 DstLink:2; ///< Destination link ID |
| UINT32 DstSubLink:1; ///< Destination sublink |
| UINT32 NP:1; ///< Non-posted |
| UINT32 MmioLimit:24; ///< MMIO limit address register bits[39:16] |
| } MMIO_LIMIT_LOW; |
| |
| /// MMIO base/limit high |
| typedef struct { |
| UINT32 MmioBase:8; ///< MMIO base address register bits[47:40] |
| UINT32 :8; ///< Reserved |
| UINT32 MmioLimit:8; ///< MMIO limit address register bits[47:40] |
| UINT32 :8; ///< Reserved |
| } MMIO_BASE_LIMIT_HI; |
| |
| /// MMIO base/limit high |
| typedef struct { |
| UINT32 RE:1; ///< Read enable |
| UINT32 WE:1; ///< Write enable |
| UINT32 DevCmpEn:1; ///< Device number compare mode enable |
| UINT32 :1; ///< Reserved |
| UINT32 DstNode:3; ///< Destination node ID bits |
| UINT32 :1; ///< Reserved |
| UINT32 DstLink:2; ///< Destination link ID |
| UINT32 DstSubLink:1; ///< Destination sublink |
| UINT32 :5; ///< Reserved |
| UINT32 BusNumBase:8; ///< Bus number base bits |
| UINT32 BusNumLimit:8; ///< Bus number limit bits |
| } CONFIGURATION_MAP; |
| |
| /*--------------------------------------------------------------------------------------- |
| * F U N C T I O N P R O T O T Y P E |
| *--------------------------------------------------------------------------------------- |
| */ |
| |
| #endif // _CPU_F15_MMIO_MAP_H_ |
