| /* $NoKeywords:$ */ |
| /** |
| * @file |
| * |
| * Install of build options for a Virgo platform solution |
| * |
| * This file generates the defaults tables for the "Virgo" platform solution |
| * set of processors. The documented build options are imported from a user |
| * controlled file for processing. |
| * |
| * @xrefitem bom "File Content Label" "Release Content" |
| * @e project: AGESA |
| * @e sub-project: Core |
| * @e \$Revision: 65876 $ @e \$Date: 2012-02-26 21:30:10 -0600 (Sun, 26 Feb 2012) $ |
| */ |
| /***************************************************************************** |
| * |
| * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. |
| * |
| * AMD is granting you permission to use this software (the Materials) |
| * pursuant to the terms and conditions of your Software License Agreement |
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| * of these Materials shall constitute your acceptance of those terms and |
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| * |
| * CONFIDENTIALITY: The Materials and all other information, identified as |
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| * |
| * You agree that you will not reverse engineer or decompile the Materials. |
| * |
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| * further information, software, technical information, know-how, or show-how |
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| * |
| * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with |
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| * subject to the restrictions as set forth in FAR 52.227-14 and |
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| * |
| * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any |
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| * |
| ***************************************************************************/ |
| |
| #include "cpuRegisters.h" |
| #include "cpuFamRegisters.h" |
| #include "cpuFamilyTranslation.h" |
| #include "AdvancedApi.h" |
| #include "heapManager.h" |
| #include "CreateStruct.h" |
| #include "cpuFeatures.h" |
| #include "Table.h" |
| #include "CommonReturns.h" |
| #include "cpuEarlyInit.h" |
| #include "cpuLateInit.h" |
| #include "GnbInterface.h" |
| |
| /***************************************************************************** |
| * Define the RELEASE VERSION string |
| * |
| * The Release Version string should identify the next planned release. |
| * When a branch is made in preparation for a release, the release manager |
| * should change/confirm that the branch version of this file contains the |
| * string matching the desired version for the release. The trunk version of |
| * the file should always contain a trailing 'X'. This will make sure that a |
| * development build from trunk will not be confused for a released version. |
| * The release manager will need to remove the trailing 'X' and update the |
| * version string as appropriate for the release. The trunk copy of this file |
| * should also be updated/incremented for the next expected version, + trailing 'X' |
| ****************************************************************************/ |
| // This is the delivery package title, "TrinyPI " |
| // This string MUST be exactly 8 characters long |
| #define AGESA_PACKAGE_STRING {'T', 'r', 'i', 'n', 'y', 'P', 'I', ' '} |
| |
| // This is the release version number of the AGESA component |
| // This string MUST be exactly 12 characters long |
| #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '2', ' ', ' ', ' ', ' '} |
| |
| |
| // The Virgo solution is defined to be family 0x15 models 0x10 - 0x1F in the FM2 socket. |
| #define INSTALL_FM2_SOCKET_SUPPORT TRUE |
| #define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE |
| |
| |
| // The following definitions specify the default values for various parameters in which there are |
| // no clearly defined defaults to be used in the common file. The values below are based on product |
| // and BKDG content, please consult the AGESA Memory team for consultation. |
| #define DFLT_SCRUB_DRAM_RATE (0) |
| #define DFLT_SCRUB_L2_RATE (0) |
| #define DFLT_SCRUB_L3_RATE (0) |
| #define DFLT_SCRUB_IC_RATE (0) |
| #define DFLT_SCRUB_DC_RATE (0) |
| #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED |
| #define DFLT_VRM_SLEW_RATE (5000) |
| |
| |
| #define DFLT_SMBUS0_BASE_ADDRESS 0xB00 |
| #define DFLT_SMBUS1_BASE_ADDRESS 0xB20 |
| #define DFLT_SIO_PME_BASE_ADDRESS 0xE00 |
| #define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 |
| #define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 |
| #define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 |
| #define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 |
| #define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x420 |
| #define DFLT_SPI_BASE_ADDRESS 0xFEC10000ul |
| #define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0ul |
| #define DFLT_HPET_BASE_ADDRESS 0xFED00000ul |
| #define DFLT_SMI_CMD_PORT 0xB0 |
| #define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 |
| #define DFLT_GEC_BASE_ADDRESS 0xFED61000ul |
| #define DFLT_SMBUS_SSID 0x780B1022ul |
| #define DFLT_IDE_SSID 0x780C1022ul |
| #define DFLT_SATA_AHCI_SSID 0x78011022ul |
| #define DFLT_SATA_IDE_SSID 0x78001022ul |
| #define DFLT_SATA_RAID5_SSID 0x78031022ul |
| #define DFLT_SATA_RAID_SSID 0x78021022ul |
| #define DFLT_EHCI_SSID 0x78081022ul |
| #define DFLT_OHCI_SSID 0x78071022ul |
| #define DFLT_LPC_SSID 0x780E1022ul |
| #define DFLT_SD_SSID 0x78061022ul |
| #define DFLT_XHCI_SSID 0x78121022ul |
| #define DFLT_FCH_PORT80_BEHIND_PCIB FALSE |
| #define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE |
| #define DFLT_FCH_GPP_LINK_CONFIG PortA4 |
| #define DFLT_FCH_GPP_PORT0_PRESENT FALSE |
| #define DFLT_FCH_GPP_PORT1_PRESENT FALSE |
| #define DFLT_FCH_GPP_PORT2_PRESENT FALSE |
| #define DFLT_FCH_GPP_PORT3_PRESENT FALSE |
| #define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE |
| #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE |
| #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE |
| #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE |
| |
| #ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT |
| #error BLDCFG: BLDCFG_VRM_INRUSH_CURRENT_LIMIT is deprecated. Use BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT instead. |
| #endif |
| |
| #ifdef BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT |
| #error BLDCFG: BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT is deprecated. Use BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT instead. |
| #endif |
| |
| // Instantiate all solution relevant data. |
| #include "PlatformInstall.h" |
| |
