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/* $NoKeywords:$ */
/**
* @file
*
* AGESA options structures
*
* Contains options control structures for the AGESA build options
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*/
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#ifndef _OPTIONS_H_
#define _OPTIONS_H_
/**
* Provide topology limits for loops and runtime, based on supported families.
*/
typedef struct {
UINT32 PlatformNumberOfSockets; ///< The limit to the number of processors based on
///< supported families and other build options.
UINT32 PlatformNumberOfModules; ///< The limit to the number of modules in a processor, based
///< on supported families.
} OPTIONS_CONFIG_TOPOLOGY;
/**
* Dispatch Table.
*
* The push high dispatcher uses this table to find what entries are currently in the build image.
*/
typedef struct {
UINT32 FunctionId; ///< The function id specified.
IMAGE_ENTRY EntryPoint; ///< The corresponding entry point to call.
} DISPATCH_TABLE;
#ifdef BLDCFG_PLATFORM_POWER_POLICY_MODE
#define CFG_PLATFORM_POWER_POLICY_MODE (BLDCFG_PLATFORM_POWER_POLICY_MODE)
#else
#define CFG_PLATFORM_POWER_POLICY_MODE (Performance)
#endif
#ifdef BLDCFG_PCI_MMIO_BASE
#define CFG_PCI_MMIO_BASE (BLDCFG_PCI_MMIO_BASE)
#else
#define CFG_PCI_MMIO_BASE (0)
#endif
#ifdef BLDCFG_PCI_MMIO_SIZE
#define CFG_PCI_MMIO_SIZE (BLDCFG_PCI_MMIO_SIZE)
#else
#define CFG_PCI_MMIO_SIZE (0)
#endif
#ifdef BLDCFG_AP_MTRR_SETTINGS_LIST
#define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST)
#else
#define CFG_AP_MTRR_SETTINGS_LIST (NULL)
#endif
#ifdef BLDCFG_IOMMU_EXCLUSION_RANGE_LIST
#define CFG_IOMMU_EXCLUSION_RANGE_LIST (BLDCFG_IOMMU_EXCLUSION_RANGE_LIST)
#else
#define CFG_IOMMU_EXCLUSION_RANGE_LIST (NULL)
#endif
#endif // _OPTIONS_H_