src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl

/**
 * @file
 *
 * ALIB ASL library
 *
 *
 *
 * @xrefitem bom "File Content Label" "Release Content"
 * @e project:     AGESA
 * @e sub-project: GNB
 * @e \$Revision: 31805 $   @e \$Date: 2010-05-21 17:58:16 -0700 (Fri, 21 May 2010) $
 *
 */
/*
 *****************************************************************************
 *
 * Copyright (c) 2011, Advanced Micro Devices, Inc.
 * All rights reserved.
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
 *       its contributors may be used to endorse or promote products derived 
 *       from this software without specific prior written permission.
 * 
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * ***************************************************************************
 *
 */

DefinitionBlock (
  "F14PcieAlibSsdt.aml",
  "SSDT",
  2,
  "AMD",
  "ALIB",
  0x1
  )
{
  Scope(\_SB) {

    Name (varMaxPortIndexNumber, 6)

    include ("PcieAlibCore.asl")
    include ("PcieSmuLibV1.asl")
    include ("PcieAlibPspp.asl")
    include ("PcieAlibHotplug.asl")

    /*----------------------------------------------------------------------------------------*/
    /**
     *  Activate DPM state
     *
     *  Arg0 	- 1 - GEN1 2 - GEN2
     *  Arg1  - 0 (AC)   1 (DC)
     */
    Method (procNbLclkDpmActivate, 2, NotSerialized) {

      Store (procSmuRcuRead (0x8490), Local0)
      // Patch state only if at least one state is enable
      if (LNotEqual (And (Local0, 0xF0), 0)) {
        if (LEqual (Arg0, 2)) {
            //If AC/DC, & Gen2 supported, activate state DPM0 and DPM2,
            //set SMUx0B_x8490[LclkDpmValid[5, 7] = 1, set SMUx0B_x8490[LclkDpmValid[6]] = 0
            //This is a battery ¡¥idle¡¦ state along with a ¡¥perf¡¦ state that will be programmed to the max LCLK achievable at the Gen2 VID
            And (Local0, 0xFFFFFFA0, Local0)
            Or (Local0, 0xA0, Local0)
          
        } else {
        	if (LEqual (Arg1, 0)) {
            //If AC, & if only Gen1 supported, activate state DPM0 and DPM1
            //set SMUx0B_x8490[LclkDpmValid[6, 5]] = 1, set SMUx0B_x8490[LclkDpmValid[7]] = 0
            And (Local0, 0xFFFFFF60, Local0)
            Or (Local0, 0x60, Local0)
          } else {
          	//If DC mode & Gen1 supported, activate only state DPM0
          	//set SMUx0B_x8490[LclkDpmValid[7, 6]] = 0, set SMUx0B_x8490[LclkDpmValid[5]] = 1
            And (Local0, 0xFFFFFF20, Local0)
            Or (Local0, 0x20, Local0)
          }
        }
        procSmuRcuWrite (0x8490, Local0)
      }
    }

#ifdef  PCIE_PHY_LANE_POWER_GATE_SUPPORT
    /*----------------------------------------------------------------------------------------*/
    /**
     *  Power gate PCIe phy lanes (hotplug support)
     *
     *  Arg0 - Start Lane ID
     *  Arg1 - End Lane ID
     *  Arg2 - Power ON(1) / OFF(0) 
     */
    Method (procPcieLanePowerControl, 3, NotSerialized) {
       // stub function
    }
#endif
    /*----------------------------------------------------------------------------------------*/
    /**
     *  Adjust PLL settings stub
     *
     *  Arg0 	- 1 - GEN1 2 - GEN2
     *  
     */
    Method (procPcieAdjustPll, 1, NotSerialized) {
      //stub function
    }
    Name (AD0B, 0)
    /*----------------------------------------------------------------------------------------*/
    /**
     *  APM/PDM stub
     *
     *  Arg0  - 0 (AC)   1 (DC)
     *
     */
    Method (procApmPdmActivate, 1, NotSerialized) {
      if (LEqual (AD0B, 1)) {
        Store (Or(ShiftLeft (0x18, 3), 4), Local1)
        Store (procPciDwordRead (Local1, 0x15C), Local2)
        if (LEqual (Arg0, DEF_PSPP_STATE_AC)) {
          Or (Local2, 0x01, Local2)
        } else {
          And (Local2, 0xfffffffc, Local2)
        }
        procPciDwordWrite (Local1, 0x15C, Local2)
      }
    }
  } //End of Scope(\_SB)
}   //End of DefinitionBlock