| /* |
| * This file is part of the coreboot project. |
| * |
| * Copyright (C) 2013 Google Inc. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| * the Free Software Foundation; version 2 of the License. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| */ |
| |
| #include <stdint.h> |
| #include <string.h> |
| #include <cbfs.h> |
| #include <console/console.h> |
| #include <baytrail/gpio.h> |
| #include <baytrail/mrc_wrapper.h> |
| #include <baytrail/romstage.h> |
| |
| /* |
| * RAM_ID[2:0] are on GPIO_SSUS[39:37] |
| * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz |
| * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz |
| * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz |
| * 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz |
| */ |
| #define SPD_SIZE 256 |
| #define GPIO_SSUS_37_PAD 57 |
| #define GPIO_SSUS_38_PAD 50 |
| #define GPIO_SSUS_39_PAD 58 |
| |
| static void *get_spd_pointer(char *spd_file_content, int total_spds) |
| { |
| int ram_id = 0; |
| |
| ram_id |= (ssus_get_gpio(GPIO_SSUS_37_PAD) << 0); |
| ram_id |= (ssus_get_gpio(GPIO_SSUS_38_PAD) << 1); |
| ram_id |= (ssus_get_gpio(GPIO_SSUS_39_PAD) << 2); |
| |
| if (ram_id >= total_spds) |
| return NULL; |
| |
| return &spd_file_content[SPD_SIZE * ram_id]; |
| } |
| |
| void mainboard_romstage_entry(struct romstage_params *rp) |
| { |
| struct cbfs_file *spd_file; |
| void *spd_content; |
| |
| struct mrc_params mp = { |
| .mainboard = { |
| .dram_type = DRAM_DDR3L, |
| .dram_info_location = DRAM_INFO_SPD_MEM, |
| }, |
| }; |
| |
| spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); |
| if (!spd_file) |
| die("SPD data not found."); |
| |
| /* Both channels are always present. */ |
| spd_content = get_spd_pointer(CBFS_SUBHEADER(spd_file), |
| ntohl(spd_file->len) / SPD_SIZE); |
| mp.mainboard.dram_data[0] = spd_content; |
| mp.mainboard.dram_data[1] = spd_content; |
| |
| rp->mrc_params = ∓ |
| romstage_common(rp); |
| } |