| # CFG Version 11 |
| # Do not edit. Generated by gen_sdram_cfg V5.0.1. Command: |
| # gen_sdram_cfg -i ddr3_256Mx16x4_H5TC4G63AFR_RDA.par 1.082 -dram_board_cfg 10 -fly_by_time_ps 1650 |
| # -b PM358/PM358_924MHz_emc_reg.txt -o PM358_Hynix_2GB_H5TC4G63AFR_RDA_924Mhz.cfg |
| # Parameter file: ddr3_256Mx16x4_H5TC4G63AFR_RDA.par, tck = 1.08 ns (924.21 MHz) |
| # bkv file: PM358/PM358_924MHz_emc_reg.txt |
| SDRAM[0].MemoryType = NvBootMemoryType_Ddr3; |
| SDRAM[0].PllMInputDivider = 0x00000001; |
| SDRAM[0].PllMFeedbackDivider = 0x0000004d; |
| SDRAM[0].PllMStableTime = 0x0000012c; |
| SDRAM[0].PllMSetupControl = 0x00000000; |
| SDRAM[0].PllMSelectDiv2 = 0x00000000; |
| SDRAM[0].PllMPDLshiftPh45 = 0x00000001; |
| SDRAM[0].PllMPDLshiftPh90 = 0x00000001; |
| SDRAM[0].PllMPDLshiftPh135 = 0x00000001; |
| SDRAM[0].PllMKCP = 0x00000000; |
| SDRAM[0].PllMKVCO = 0x00000000; |
| SDRAM[0].EmcBctSpare0 = 0x00000000; |
| SDRAM[0].EmcBctSpare1 = 0x00000000; |
| SDRAM[0].EmcBctSpare2 = 0x00000000; |
| SDRAM[0].EmcBctSpare3 = 0x00000000; |
| SDRAM[0].EmcBctSpare4 = 0x00000000; |
| SDRAM[0].EmcBctSpare5 = 0x00000000; |
| SDRAM[0].EmcBctSpare6 = 0x00000000; |
| SDRAM[0].EmcBctSpare7 = 0x00000000; |
| SDRAM[0].EmcBctSpare8 = 0x00000000; |
| SDRAM[0].EmcBctSpare9 = 0x00000000; |
| SDRAM[0].EmcBctSpare10 = 0x00000000; |
| SDRAM[0].EmcBctSpare11 = 0x00000000; |
| SDRAM[0].EmcClockSource = 0x80000000; |
| SDRAM[0].EmcAutoCalInterval = 0x001fffff; |
| SDRAM[0].EmcAutoCalConfig = 0xa1430404; |
| SDRAM[0].EmcAutoCalConfig2 = 0x00000000; |
| SDRAM[0].EmcAutoCalConfig3 = 0x00000000; |
| SDRAM[0].EmcAutoCalWait = 0x00000190; |
| SDRAM[0].EmcAdrCfg = 0x00000000; |
| SDRAM[0].EmcPinProgramWait = 0x00000001; |
| SDRAM[0].EmcPinExtraWait = 0x00000000; |
| SDRAM[0].EmcTimingControlWait = 0x00000000; |
| SDRAM[0].EmcRc = 0x0000002b; |
| SDRAM[0].EmcRfc = 0x000000ef; |
| SDRAM[0].EmcRfcSlr = 0x00000000; |
| SDRAM[0].EmcRas = 0x0000001e; |
| SDRAM[0].EmcRp = 0x0000000b; |
| SDRAM[0].EmcR2r = 0x00000000; |
| SDRAM[0].EmcW2w = 0x00000000; |
| SDRAM[0].EmcR2w = 0x00000008; |
| SDRAM[0].EmcW2r = 0x0000000f; |
| SDRAM[0].EmcR2p = 0x00000005; |
| SDRAM[0].EmcW2p = 0x00000016; |
| SDRAM[0].EmcRdRcd = 0x0000000b; |
| SDRAM[0].EmcWrRcd = 0x0000000b; |
| SDRAM[0].EmcRrd = 0x00000004; |
| SDRAM[0].EmcRext = 0x00000002; |
| SDRAM[0].EmcWext = 0x00000000; |
| SDRAM[0].EmcWdv = 0x00000006; |
| SDRAM[0].EmcWdvMask = 0x00000006; |
| SDRAM[0].EmcQUse = 0x0000000c; |
| SDRAM[0].EmcQuseWidth = 0x00000002; |
| SDRAM[0].EmcIbdly = 0x00000000; |
| SDRAM[0].EmcEInput = 0x00000002; |
| SDRAM[0].EmcEInputDuration = 0x0000000e; |
| SDRAM[0].EmcPutermExtra = 0x000a0000; |
| SDRAM[0].EmcPutermWidth = 0x00000004; |
| SDRAM[0].EmcPutermAdj = 0x00000000; |
| SDRAM[0].EmcCdbCntl1 = 0x00000000; |
| SDRAM[0].EmcCdbCntl2 = 0x00000000; |
| SDRAM[0].EmcCdbCntl3 = 0x00000000; |
| SDRAM[0].EmcQRst = 0x00000001; |
| SDRAM[0].EmcQSafe = 0x00000015; |
| SDRAM[0].EmcRdv = 0x0000001b; |
| SDRAM[0].EmcRdvMask = 0x0000001d; |
| SDRAM[0].EmcQpop = 0x00000010; |
| SDRAM[0].EmcCtt = 0x00000000; |
| SDRAM[0].EmcCttDuration = 0x00000004; |
| SDRAM[0].EmcRefresh = 0x00001be9; |
| SDRAM[0].EmcBurstRefreshNum = 0x00000000; |
| SDRAM[0].EmcPreRefreshReqCnt = 0x000006fa; |
| SDRAM[0].EmcPdEx2Wr = 0x00000004; |
| SDRAM[0].EmcPdEx2Rd = 0x00000015; |
| SDRAM[0].EmcPChg2Pden = 0x00000001; |
| SDRAM[0].EmcAct2Pden = 0x00000000; |
| SDRAM[0].EmcAr2Pden = 0x000000e6; |
| SDRAM[0].EmcRw2Pden = 0x0000001b; |
| SDRAM[0].EmcTxsr = 0x000000fa; |
| SDRAM[0].EmcTxsrDll = 0x00000200; |
| SDRAM[0].EmcTcke = 0x00000006; |
| SDRAM[0].EmcTckesr = 0x00000007; |
| SDRAM[0].EmcTpd = 0x00000006; |
| SDRAM[0].EmcTfaw = 0x00000022; |
| SDRAM[0].EmcTrpab = 0x00000000; |
| SDRAM[0].EmcTClkStable = 0x0000000a; |
| SDRAM[0].EmcTClkStop = 0x0000000a; |
| SDRAM[0].EmcTRefBw = 0x00001c29; |
| SDRAM[0].EmcFbioCfg5 = 0x104ab898; |
| SDRAM[0].EmcFbioCfg6 = 0x00000002; |
| SDRAM[0].EmcFbioSpare = 0x00000000; |
| SDRAM[0].EmcCfgRsv = 0xff00ff00; |
| SDRAM[0].EmcMrs = 0x80000f15; |
| SDRAM[0].EmcEmrs = 0x80100002; |
| SDRAM[0].EmcEmrs2 = 0x80200020; |
| SDRAM[0].EmcEmrs3 = 0x80300000; |
| SDRAM[0].EmcMrw1 = 0x00000000; |
| SDRAM[0].EmcMrw2 = 0x00000000; |
| SDRAM[0].EmcMrw3 = 0x00000000; |
| SDRAM[0].EmcMrw4 = 0x00000000; |
| SDRAM[0].EmcMrwExtra = 0x00000000; |
| SDRAM[0].EmcWarmBootMrwExtra = 0x00000000; |
| SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000; |
| SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000; |
| SDRAM[0].EmcMrwResetCommand = 0x00000000; |
| SDRAM[0].EmcMrwResetNInitWait = 0x00000000; |
| SDRAM[0].EmcMrsWaitCnt = 0x00ce000e; |
| SDRAM[0].EmcMrsWaitCnt2 = 0x00ce000e; |
| SDRAM[0].EmcCfg = 0x73300000; |
| SDRAM[0].EmcCfg2 = 0x000008a5; |
| SDRAM[0].EmcCfgPipe = 0x00000000; |
| SDRAM[0].EmcDbg = 0x01000c00; |
| SDRAM[0].EmcCmdQ = 0x10004408; |
| SDRAM[0].EmcMc2EmcQ = 0x06000404; |
| SDRAM[0].EmcDynSelfRefControl = 0x800037ed; |
| SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001; |
| SDRAM[0].EmcCfgDigDll = 0xe00401b1; |
| SDRAM[0].EmcCfgDigDllPeriod = 0x00008000; |
| SDRAM[0].EmcDevSelect = 0x00000002; |
| SDRAM[0].EmcSelDpdCtrl = 0x00040000; |
| SDRAM[0].EmcDllXformDqs0 = 0x00000005; |
| SDRAM[0].EmcDllXformDqs1 = 0x00000005; |
| SDRAM[0].EmcDllXformDqs2 = 0x00000005; |
| SDRAM[0].EmcDllXformDqs3 = 0x00000005; |
| SDRAM[0].EmcDllXformDqs4 = 0x00000005; |
| SDRAM[0].EmcDllXformDqs5 = 0x00000005; |
| SDRAM[0].EmcDllXformDqs6 = 0x00000005; |
| SDRAM[0].EmcDllXformDqs7 = 0x00000005; |
| SDRAM[0].EmcDllXformDqs8 = 0x00000005; |
| SDRAM[0].EmcDllXformDqs9 = 0x00000005; |
| SDRAM[0].EmcDllXformDqs10 = 0x00000005; |
| SDRAM[0].EmcDllXformDqs11 = 0x00000005; |
| SDRAM[0].EmcDllXformDqs12 = 0x00000005; |
| SDRAM[0].EmcDllXformDqs13 = 0x00000005; |
| SDRAM[0].EmcDllXformDqs14 = 0x00000005; |
| SDRAM[0].EmcDllXformDqs15 = 0x00000005; |
| SDRAM[0].EmcDllXformQUse0 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse1 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse2 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse3 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse4 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse5 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse6 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse7 = 0x00000000; |
| SDRAM[0].EmcDllXformAddr0 = 0x0000400e; |
| SDRAM[0].EmcDllXformAddr1 = 0x0000400e; |
| SDRAM[0].EmcDllXformAddr2 = 0x00000000; |
| SDRAM[0].EmcDllXformAddr3 = 0x0000400e; |
| SDRAM[0].EmcDllXformAddr4 = 0x0000400e; |
| SDRAM[0].EmcDllXformAddr5 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse8 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse9 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse10 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse11 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse12 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse13 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse14 = 0x00000000; |
| SDRAM[0].EmcDllXformQUse15 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs8 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs9 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs10 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs11 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs12 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs13 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs14 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs15 = 0x00000000; |
| SDRAM[0].EmcDllXformDq0 = 0x00000006; |
| SDRAM[0].EmcDllXformDq1 = 0x00000006; |
| SDRAM[0].EmcDllXformDq2 = 0x00000006; |
| SDRAM[0].EmcDllXformDq3 = 0x00000006; |
| SDRAM[0].EmcDllXformDq4 = 0x00000006; |
| SDRAM[0].EmcDllXformDq5 = 0x00000006; |
| SDRAM[0].EmcDllXformDq6 = 0x00000006; |
| SDRAM[0].EmcDllXformDq7 = 0x00000006; |
| SDRAM[0].WarmBootWait = 0x00000002; |
| SDRAM[0].EmcCttTermCtrl = 0x00000802; |
| SDRAM[0].EmcOdtWrite = 0x00000000; |
| SDRAM[0].EmcOdtRead = 0x00000000; |
| SDRAM[0].EmcZcalInterval = 0x00020000; |
| SDRAM[0].EmcZcalWaitCnt = 0x0000004c; |
| SDRAM[0].EmcZcalMrwCmd = 0x80000000; |
| SDRAM[0].EmcMrsResetDll = 0x00000000; |
| SDRAM[0].EmcZcalInitDev0 = 0x80000011; |
| SDRAM[0].EmcZcalInitDev1 = 0x00000000; |
| SDRAM[0].EmcZcalInitWait = 0x00000001; |
| SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003; |
| SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab; |
| SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000; |
| SDRAM[0].EmcZcalWarmBootWait = 0x00000001; |
| SDRAM[0].EmcMrsWarmBootEnable = 0x00000001; |
| SDRAM[0].EmcMrsResetDllWait = 0x00000000; |
| SDRAM[0].EmcMrsExtra = 0x80000f15; |
| SDRAM[0].EmcWarmBootMrsExtra = 0x80100002; |
| SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000; |
| SDRAM[0].EmcMrsDdr2DllReset = 0x00000000; |
| SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000; |
| SDRAM[0].EmcDdr2Wait = 0x00000000; |
| SDRAM[0].EmcClkenOverride = 0x00000000; |
| SDRAM[0].McDisExtraSnapLevels = 0x00000000; |
| SDRAM[0].EmcExtraRefreshNum = 0x00000002; |
| SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000; |
| SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000; |
| SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003; |
| SDRAM[0].PmcVddpSel = 0x00000002; |
| SDRAM[0].PmcVddpSelWait = 0x00000002; |
| SDRAM[0].PmcDdrPwr = 0x00000003; |
| SDRAM[0].PmcDdrCfg = 0x00002002; |
| SDRAM[0].PmcIoDpd3Req = 0x4fff2f97; |
| SDRAM[0].PmcIoDpd3ReqWait = 0x00000000; |
| SDRAM[0].PmcRegShort = 0x00000000; |
| SDRAM[0].PmcNoIoPower = 0x00000000; |
| SDRAM[0].PmcPorDpdCtrlWait = 0x00000000; |
| SDRAM[0].EmcXm2CmdPadCtrl = 0x100002a0; |
| SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000; |
| SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000; |
| SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000; |
| SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00111111; |
| SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414; |
| SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0020013d; |
| SDRAM[0].EmcXm2DqsPadCtrl3 = 0x55555520; |
| SDRAM[0].EmcXm2DqsPadCtrl4 = 0x003cf3cf; |
| SDRAM[0].EmcXm2DqsPadCtrl5 = 0x003cf3cf; |
| SDRAM[0].EmcXm2DqsPadCtrl6 = 0x55555500; |
| SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990; |
| SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000; |
| SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000; |
| SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc085; |
| SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000303; |
| SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108; |
| SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070004; |
| SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x00000000; |
| SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x016eeeee; |
| SDRAM[0].EmcAcpdControl = 0x00000000; |
| SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00003120; |
| SDRAM[0].EmcSwizzleRank0Byte0 = 0x25143067; |
| SDRAM[0].EmcSwizzleRank0Byte1 = 0x45367102; |
| SDRAM[0].EmcSwizzleRank0Byte2 = 0x47106253; |
| SDRAM[0].EmcSwizzleRank0Byte3 = 0x04362175; |
| SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003120; |
| SDRAM[0].EmcSwizzleRank1Byte0 = 0x71546032; |
| SDRAM[0].EmcSwizzleRank1Byte1 = 0x35104276; |
| SDRAM[0].EmcSwizzleRank1Byte2 = 0x27043615; |
| SDRAM[0].EmcSwizzleRank1Byte3 = 0x72306145; |
| SDRAM[0].EmcDsrVttgenDrv = 0x0606003f; |
| SDRAM[0].EmcTxdsrvttgen = 0x00000000; |
| SDRAM[0].EmcBgbiasCtl0 = 0x00000000; |
| SDRAM[0].McEmemAdrCfg = 0x00000000; |
| SDRAM[0].McEmemAdrCfgDev0 = 0x00080303; |
| SDRAM[0].McEmemAdrCfgDev1 = 0x00080303; |
| SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248; |
| SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490; |
| SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920; |
| SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001; |
| SDRAM[0].McEmemCfg = 0x00000800; |
| SDRAM[0].McEmemArbCfg = 0x0e00000d; |
| SDRAM[0].McEmemArbOutstandingReq = 0x80000040; |
| SDRAM[0].McEmemArbTimingRcd = 0x00000005; |
| SDRAM[0].McEmemArbTimingRp = 0x00000006; |
| SDRAM[0].McEmemArbTimingRc = 0x00000016; |
| SDRAM[0].McEmemArbTimingRas = 0x0000000e; |
| SDRAM[0].McEmemArbTimingFaw = 0x00000011; |
| SDRAM[0].McEmemArbTimingRrd = 0x00000002; |
| SDRAM[0].McEmemArbTimingRap2Pre = 0x00000004; |
| SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000e; |
| SDRAM[0].McEmemArbTimingR2R = 0x00000002; |
| SDRAM[0].McEmemArbTimingW2W = 0x00000002; |
| SDRAM[0].McEmemArbTimingR2W = 0x00000006; |
| SDRAM[0].McEmemArbTimingW2R = 0x00000009; |
| SDRAM[0].McEmemArbDaTurns = 0x09060202; |
| SDRAM[0].McEmemArbDaCovers = 0x001a1016; |
| SDRAM[0].McEmemArbMisc0 = 0x734e2a17; |
| SDRAM[0].McEmemArbMisc1 = 0x70000f02; |
| SDRAM[0].McEmemArbRing1Throttle = 0x001f0000; |
| SDRAM[0].McEmemArbOverride = 0x10000000; |
| SDRAM[0].McEmemArbOverride1 = 0x00000000; |
| SDRAM[0].McEmemArbRsv = 0xff00ff00; |
| SDRAM[0].McClkenOverride = 0x00000000; |
| SDRAM[0].McStatControl = 0x00000000; |
| SDRAM[0].McDisplaySnapRing = 0x00000003; |
| SDRAM[0].McVideoProtectBom = 0xfff00000; |
| SDRAM[0].McVideoProtectBomAdrHi = 0x00000000; |
| SDRAM[0].McVideoProtectSizeMb = 0x00000000; |
| SDRAM[0].McVideoProtectVprOverride = 0xe4bac743; |
| SDRAM[0].McVideoProtectVprOverride1 = 0x00000013; |
| SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000; |
| SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000; |
| SDRAM[0].McSecCarveoutBom = 0xfff00000; |
| SDRAM[0].McSecCarveoutAdrHi = 0x00000000; |
| SDRAM[0].McSecCarveoutSizeMb = 0x00000000; |
| SDRAM[0].McVideoProtectWriteAccess = 0x00000000; |
| SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000; |
| SDRAM[0].EmcCaTrainingEnable = 0x00000000; |
| SDRAM[0].EmcCaTrainingTimingCntl1 = 0x1f7df7df; |
| SDRAM[0].EmcCaTrainingTimingCntl2 = 0x0000001f; |
| SDRAM[0].SwizzleRankByteEncode = 0x0000006f; |
| SDRAM[0].BootRomPatchControl = 0x00000000; |
| SDRAM[0].BootRomPatchData = 0x00000000; |
| SDRAM[0].McMtsCarveoutBom = 0xfff00000; |
| SDRAM[0].McMtsCarveoutAdrHi = 0x00000000; |
| SDRAM[0].McMtsCarveoutSizeMb = 0x00000000; |
| SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000; |
| #@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000017; |
| #@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x000001bb; |
| #@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x006e0038; |
| #@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x006e0038; |
| #@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x006e003c; |
| #@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x006e0090; |
| #@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x006e0041; |
| #@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x006e0090; |
| #@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x006e0041; |
| #@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049; |
| #@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x006e0080; |
| #@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x006e0004; |
| #@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x006e0004; |
| #@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016; |
| #@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x0000006e; |
| #@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x006e0004; |
| #@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x006e0019; |
| #@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x006e0018; |
| #@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x006e0024; |
| #@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x006e001b; |
| #@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x0000006e; |
| #@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036; |
| #@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x006e006e; |
| #@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036; |
| #@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x006e006e; |
| #@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff; |
| #@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029; |
| #@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x006e006e; |
| #@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x006e006e; |
| #@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x006e0065; |
| #@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x006e001c; |
