#
# This file is part of the coreboot project.
#
# Copyright (C) 2011 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
chip northbridge/amd/agesa/family14/root_complex
        device cpu_cluster 0 on
                chip cpu/amd/agesa/family14
                  device lapic 0 on end
                end
        end
        device domain 0 on
                subsystemid 0x1022 0x1510 inherit
                chip northbridge/amd/agesa/family14 # CPU side of HT root complex
#                       device pci 18.0 on #  northbridge
                                chip northbridge/amd/agesa/family14 # PCI side of HT root complex
                                        device pci 0.0 on end # Root Complex
                                        device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
                                        device pci 1.1 on end # Internal HDMI Audio
                                        device pci 4.0 on end # PCIE P2P bridge 0x9604
                                        device pci 5.0 on end # PCIE P2P bridge 0x9605
                                        device pci 6.0 on end # PCIE P2P bridge 0x9606
                                        device pci 7.0 on end # PCIE P2P bridge 0x9607
                                        device pci 8.0 on end # NB/SB Link P2P bridge
                                end # agesa northbridge

                                chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
                                        device pci 11.0 on end # SATA
                                        device pci 12.0 on end # USB
                                        device pci 12.1 on end # USB
                                        device pci 12.2 on end # USB
                                        device pci 13.0 on end # USB
                                        device pci 13.1 on end # USB
                                        device pci 13.2 on end # USB
                                        device pci 14.0 on # SM
##                                                chip drivers/generic/generic #dimm 0-0-0
##                                                        device i2c 50 on end
##                                                end
##                                                chip drivers/generic/generic #dimm 0-0-1
##                                                        device i2c 51 on end
##                                                end
                                        end # SM
                                        device pci 14.1 on end # IDE    0x439c
                                        device pci 14.2 on end # HDA    0x4383
                                        device pci 14.3 on # LPC        0x439d
					end #LPC
					device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
	  				device pci 14.5 on  end # USB 2
					device pci 15.0 off end # PCIe PortA
					device pci 15.1 off end # PCIe PortB
					device pci 15.2 off end # PCIe PortC
					device pci 15.3 off end # PCIe PortD
					device pci 16.0 off end # OHCI USB3
					device pci 16.2 off end # EHCI USB3
					register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
		  			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
				end	#southbridge/amd/cimx/sb800
#                       end #  device pci 18.0
# These seem unnecessary
                        device pci 18.1 on end
                        device pci 18.2 on end
                        device pci 18.3 on end
                        device pci 18.4 on end
                        device pci 18.5 on end

                        register "spdAddrLookup" = "
                        {
                            { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
                            { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
                        }"

                end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
        end #domain
end #northbridge/amd/agesa/family14/root_complex