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coreboot
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796af17f18554380a49d69d7768ac18ee039d711
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.
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src
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cpu
/
x86
/
tsc
/
Makefile.inc
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ramstage
-
$
(
CONFIG_UDELAY_TSC
)
+=
delay_tsc
.
c
romstage
-
$
(
CONFIG_TSC_CONSTANT_RATE
)
+=
delay_tsc
.
c
ifeq
(
$
(
CONFIG_HAVE_SMI_HANDLER
),
y
)
smm
-
$
(
CONFIG_TSC_CONSTANT_RATE
)
+=
delay_tsc
.
c
endif
