commit | 2a592b7fe2bc2b79ef012412619959ae3984ca78 | [log] [tgz] |
---|---|---|
author | Felix Held <felix-coreboot@felixheld.de> | Mon Mar 07 17:03:27 2022 +0100 |
committer | Commit Bot <commit-bot@chromium.org> | Mon Mar 21 22:28:53 2022 +0000 |
tree | b00c425688dbcc8eb7f1e21ea0b5d9b93867b63e | |
parent | bef02d29b569595aba5fcedd303711daa2e4692a [diff] |
UPSTREAM: mb/amd/chausie/devicetree: set PSPP policy to DXIO_PSPP_DISABLED Right now, the PSPP policy that controls if the PCIe lanes can be dynamically downgraded to a lower speed to save some power needs to be disabled in order for the link training to be successful. Once this feature is working, the PSPP policy will be switched to balanced again. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Original-Change-Id: I85a06f322c4ddff25c3a858e2b79c84b36c48932 GitOrigin-RevId: b9ee6f351b4552f024edee3f1e1d72a4a09ec45a Change-Id: I4393dc444bbd0e513330e00bb4600f361b893de6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3538523 Tested-by: CopyBot Service Account <copybot.service@gmail.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.