chip soc/intel/cannonlake

	# GPE configuration
	# Note that GPE events called out in ASL code rely on this
	# route. i.e. If this route changes then the affected GPE
	# offset bits also need to be changed.
	register "gpe0_dw0" = "PMC_GPP_A"
	register "gpe0_dw1" = "PMC_GPP_C"
	register "gpe0_dw2" = "PMC_GPP_D"

	# EC host command ranges
	register "gen1_dec" = "0x00040931" # 0x930-0x937
	register "gen2_dec" = "0x00040941" # 0x940-0x947
	register "gen3_dec" = "0x000c0951" # 0x950-0x95f

	# FSP configuration
	register "SaGv" = "SaGv_Enabled"
	register "HeciEnabled" = "1"
	register "SataSalpSupport" = "1"
	register "SataMode" = "Sata_AHCI"
	register "SataPortsEnable[2]" = "1"
	register "SataPortsDevSlp[2]" = "1"
	register "InternalGfx" = "1"
	register "SkipExtGfxScan" = "1"
	register "PchPmSlpS3MinAssert" = "3"  # 50ms
	register "PchPmSlpS4MinAssert" = "4"  # 4s
	register "PchPmSlpSusMinAssert" = "4" # 4s
	register "PchPmSlpAMinAssert" = "4"   # 2s
	register "PchUnlockGpioPads" = "1"
	register "Heci1Disabled" = "1"
	# USB2 PHY Power gating
	register "PchUsb2PhySusPgDisable" = "1"

	register "speed_shift_enable" = "1"
	register "psys_pmax" = "140"
	register "s0ix_enable" = "1"
	register "dptf_enable" = "1"
	register "dmipwroptimize" = "1"
	register "satapwroptimize" = "1"
	register "tdp_pl1_override" = "25"
	register "tdp_pl2_override" = "51"
	register "Device4Enable" = "1"
	register "AcousticNoiseMitigation" = "1"
	register "SlowSlewRateForIa" = "2"
	register "SlowSlewRateForGt" = "2"
	register "SlowSlewRateForSa" = "0"
	register "SlowSlewRateForFivr" = "2"
	# Enable eDP device
	register "DdiPortEdp" = "1"
	# Enable HPD for DDI ports B/C
	register "DdiPortBHpd" = "1"
	register "DdiPortCHpd" = "1"
	# Enable DDC for DDI port B
	register "DdiPortBDdc" = "1"

	# VR Settings Configuration for 4 Domains
	#+----------------+-------+-------+-------+-------+
	#| Domain/Setting |  SA   |  IA   | GTUS  |  GTS  |
	#+----------------+-------+-------+-------+-------+
	#| Psi1Threshold  | 20A   | 20A   | 20A   | 20A   |
	#| Psi2Threshold  | 5A    | 5A    | 5A    | 5A    |
	#| Psi3Threshold  | 1A    | 1A    | 1A    | 1A    |
	#| Psi3Enable     | 1     | 1     | 1     | 1     |
	#| Psi4Enable     | 1     | 1     | 1     | 1     |
	#| ImonSlope      | 0     | 0     | 0     | 0     |
	#| ImonOffset     | 0     | 0     | 0     | 0     |
	#| IccMax         | 6A    | 70A   | 31A   | 31A   |
	#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
	#| AcLoadline     | 10.3  | 1.8   | 3.1   | 3.1   |
	#| DcLoadline     | 10.3  | 1.8   | 3.1   | 3.1   |
	#+----------------+-------+-------+-------+-------+
	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
		.vr_config_enable = 1,
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(5),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1,
		.psi4enable = 1,
		.imon_slope = 0x0,
		.imon_offset = 0x0,
		.icc_max = VR_CFG_AMP(6),
		.voltage_limit = 1520,
		.ac_loadline = 1030,
		.dc_loadline = 1030,
	}"

	register "domain_vr_config[VR_IA_CORE]" = "{
		.vr_config_enable = 1,
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(5),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1,
		.psi4enable = 1,
		.imon_slope = 0x0,
		.imon_offset = 0x0,
		.icc_max = VR_CFG_AMP(70),
		.voltage_limit = 1520,
		.ac_loadline = 180,
		.dc_loadline = 180,
	}"

	register "domain_vr_config[VR_GT_UNSLICED]" = "{
		.vr_config_enable = 1,
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(5),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1,
		.psi4enable = 1,
		.imon_slope = 0x0,
		.imon_offset = 0x0,
		.icc_max = VR_CFG_AMP(31),
		.voltage_limit = 1520,
		.ac_loadline = 310,
		.dc_loadline = 310,
	}"

	register "domain_vr_config[VR_GT_SLICED]" = "{
		.vr_config_enable = 1,
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(5),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1,
		.psi4enable = 1,
		.imon_slope = 0x0,
		.imon_offset = 0x0,
		.icc_max = VR_CFG_AMP(31),
		.voltage_limit = 1520,
		.ac_loadline = 310,
		.dc_loadline = 310,
	}"

	# Intel Common SoC Config
	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Left Type-C Port
	register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)"	# Left Type-A Port
	register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)"	# Right Type-A Port
	register "usb2_ports[3]" = "USB2_PORT_EMPTY"
	register "usb2_ports[4]" = "USB2_PORT_EMPTY"
	register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)"	# Camera
	register "usb2_ports[6]" = "{
		.enable        = 1, \
		.ocpin         = OC_SKIP, \
		.tx_bias       = USB2_BIAS_0MV, \
		.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \
		.pre_emp_bias  = USB2_BIAS_28P15MV, \
		.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP, \
		}"	# WWAN
	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# USH
	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"	# Fingerprint
	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth

	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Left Type-C Port
	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"	# Left Type-A Port
	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)"	# Right Type-A Port
	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# WWAN
	register "usb3_ports[4]" = "USB3_PORT_EMPTY"
	register "usb3_ports[5]" = "USB3_PORT_EMPTY"

	# Intel Common SoC Config
	#+-------------------+---------------------------+
	#| Field             |  Value                    |
	#+-------------------+---------------------------+
	#| chipset_lockdown  | CHIPSET_LOCKDOWN_COREBOOT |
	#| I2C0              | Touchscreen               |
	#| I2C1              | Touchpad                  |
	#| I2C4              | H1 TPM                    |
	#+-------------------+---------------------------+

	register "tcc_offset" = "1"

	register "common_soc_config" = "{
		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
		.i2c[0] = {
			.speed = I2C_SPEED_FAST,
			.rise_time_ns = 52,
			.fall_time_ns = 110,
		},
		.i2c[1] = {
			.speed = I2C_SPEED_FAST,
			.rise_time_ns = 52,
			.fall_time_ns = 110,
			.data_hold_time_ns = 330,
		},
		.i2c[4] = {
			.early_init = 1,
			.speed = I2C_SPEED_FAST,
			.rise_time_ns = 36,
			.fall_time_ns = 99,
		},
	}"

	# PCIe port 10 for M.2 2230 WLAN
	register "PcieRpEnable[9]" = "1"
	register "PcieClkSrcUsage[2]" = "9"
	register "PcieClkSrcClkReq[2]" = "2"

	# PCIe port 11 for card reader
	register "PcieRpEnable[10]" = "1"
	register "PcieRpLtrEnable[10]" = "1"
	register "PcieClkSrcUsage[1]" = "10"
	register "PcieClkSrcClkReq[1]" = "1"

	# PCIe port 13 for M.2 2280 SSD
	register "PcieRpEnable[12]" = "1"
	register "PcieRpLtrEnable[12]" = "1"
	register "PcieClkSrcUsage[4]" = "12"
	register "PcieClkSrcClkReq[4]" = "4"

	# GPIO PM programming
	register "gpio_override_pm" = "1"

	# GPIO community PM configuration
	register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
	register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN"
	register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
	register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
	register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"

	device cpu_cluster 0 on
		device lapic 0 on end
	end
	device domain 0 on
		device pci 00.0 on  end # Host Bridge
		device pci 02.0 on  end # Integrated Graphics Device
		device pci 04.0 on  end # SA Thermal device
		device pci 12.0 on  end # Thermal Subsystem
		device pci 12.5 off end # UFS SCS
		device pci 12.6 off end # GSPI #2
		device pci 13.0 on	# Integrated Sensor Hub
			chip drivers/intel/ish
				register "firmware_name" = ""arcada_ish.bin""
				device generic 0 on end
			end
		end
		device pci 14.0 on
			chip drivers/usb/acpi
				register "desc" = ""Root Hub""
				register "type" = "UPC_TYPE_HUB"
				device usb 0.0 on
					chip drivers/usb/acpi
						register "desc" = ""Left Type-C Port""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						register "group" = "ACPI_PLD_GROUP(1, 1)"
						device usb 2.0 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""Left Type-A Port""
						register "type" = "UPC_TYPE_A"
						register "group" = "ACPI_PLD_GROUP(1, 2)"
						device usb 2.1 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""Right Type-A Port""
						register "type" = "UPC_TYPE_A"
						register "group" = "ACPI_PLD_GROUP(2, 1)"
						device usb 2.2 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""Camera""
						register "type" = "UPC_TYPE_INTERNAL"
						device usb 2.5 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""WWAN""
						register "type" = "UPC_TYPE_INTERNAL"
						device usb 2.6 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USH""
						register "type" = "UPC_TYPE_INTERNAL"
						device usb 2.7 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""Fingerprint""
						register "type" = "UPC_TYPE_INTERNAL"
						device usb 2.8 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""Bluetooth""
						register "type" = "UPC_TYPE_INTERNAL"
						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H15)"
						device usb 2.9 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""Left Type-C Port""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						register "group" = "ACPI_PLD_GROUP(1, 1)"
						device usb 3.0 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""Left Type-A Port""
						register "type" = "UPC_TYPE_USB3_A"
						register "group" = "ACPI_PLD_GROUP(1, 2)"
						device usb 3.1 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""Right Type-A Port""
						register "type" = "UPC_TYPE_USB3_A"
						register "group" = "ACPI_PLD_GROUP(2, 1)"
						device usb 3.2 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""WWAN""
						register "type" = "UPC_TYPE_INTERNAL"
						device usb 3.3 on end
					end
				end
			end
		end # USB xHCI
		device pci 14.1 off end # USB xDCI (OTG)
		chip drivers/intel/wifi
			register "wake" = "PME_B0_EN_BIT"
			device pci 14.3 on  end # CNVi wifi
		end
		device pci 14.5 off end # SDCard
		device pci 15.0 on
			chip drivers/i2c/hid
				register "generic.hid" = ""WCOM48E2""
				register "generic.desc" = ""Wacom Touchscreen""
				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)"
				register "generic.probed" = "1"
				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)"
				register "generic.reset_delay_ms" = "120"
				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
				register "generic.enable_delay_ms" = "55"
				register "generic.has_power_resource" = "1"
				register "generic.disable_gpio_export_in_crs" = "1"
				register "hid_desc_reg_offset" = "0x1"
				device i2c 0A on end
			end
		end # I2C #0
		device pci 15.1 on
			chip drivers/i2c/generic
				register "hid" = ""ELAN0000""
				register "desc" = ""ELAN Touchpad""
				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"
				register "probed" = "1"
				device i2c 2c on end
			end
			chip drivers/i2c/hid
			        register "generic.hid" = ""PNP0C50""
				register "generic.desc" = ""Cirque Touchpad""
				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"
				register "generic.probed" = "1"
				register "hid_desc_reg_offset" = "0x20"
				device i2c 2a on end
			end
		end # I2C #1
		device pci 15.2 off end # I2C #2
		device pci 15.3 off end # I2C #3
		device pci 16.0 on  end # Management Engine Interface 1
		device pci 16.1 off end # Management Engine Interface 2
		device pci 16.2 off end # Management Engine IDE-R
		device pci 16.3 off end # Management Engine KT Redirection
		device pci 16.4 off end # Management Engine Interface 3
		device pci 16.5 off end # Management Engine Interface 4
		device pci 17.0 on  end # SATA
		device pci 19.0 on
			chip drivers/i2c/tpm
				register "hid" = ""GOOG0005""
				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D18_IRQ)"
				device i2c 50 on end
			end
		end # I2C #4
		device pci 19.1 off end # I2C #5
		device pci 19.2 on  end # UART #2
		device pci 1a.0 off end # eMMC
		device pci 1c.0 off end # PCI Express Port 1 (USB)
		device pci 1c.1 off end # PCI Express Port 2 (USB)
		device pci 1c.2 off end # PCI Express Port 3 (USB)
		device pci 1c.3 off end # PCI Express Port 4 (USB)
		device pci 1c.4 off end # PCI Express Port 5 (USB)
		device pci 1c.5 off end # PCI Express Port 6
		device pci 1c.6 off end # PCI Express Port 7
		device pci 1c.7 off end # PCI Express Port 8
		device pci 1d.0 on
			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
		end # PCI Express Port 9
		device pci 1d.1 on  end # PCI Express Port 10
		device pci 1d.2 on  end # PCI Express Port 11
		device pci 1d.3 off end # PCI Express Port 12
		device pci 1d.4 on
			chip drivers/generic/bayhub
				register "power_saving" = "1"
				device pci 00.0 on end
			end
			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
		end # PCI Express Port 13 (x4)
		device pci 1e.0 off end # UART #0
		device pci 1e.1 off end # UART #1
		device pci 1e.2 off end # GSPI #0
		device pci 1e.3 off end # GSPI #1
		device pci 1f.0 on
			chip ec/google/wilco
				device pnp 0c09.0 on end
			end
		end # LPC/eSPI
		device pci 1f.1 on  end # P2SB
		device pci 1f.2 on  end # Power Management Controller
		device pci 1f.3 on  end # Intel HDA
		device pci 1f.4 on  end # SMBus
		device pci 1f.5 on  end # PCH SPI
		device pci 1f.6 off end # GbE
	end
end