tree 59ac88eb4e995f4f9ba90b3c71607bb7cc962084
parent f3b19b592bf1505fbbd32e806daeb676f90c9333
author Kane Chen <kane.chen@intel.com> 1507169827 +0800
committer chrome-bot <chrome-bot@chromium.org> 1507931069 -0700

UPSTREAM: soc/intel/skylake: Enable bus master for sata

The bus master needs to be enabled so that
the busy bit in AHCI PORT_TFDATA will be cleared
by controller when depthcharge tries to wait
for sata to complete spin-up during AHCI init.

Otherwise, the timeout will happen and cause
5 seconds delay in depthcharge.

BUG=b:37639063
BRANCH=none
TEST=verify that the sata timeout is gone in
     depthcharge

Change-Id: If95b4e11b8de302e7135276191f0e249b4eec0ce
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f73bc0b2d103705a557142461d19496b59adda81
Original-Change-Id: I19eadbb2943fda8a5babc82ca87b1ecaab5e2ed8
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://review.coreboot.org/21890
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/716221
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>