diff --git a/src/soc/intel/baytrail/baytrail/romstage.h b/src/soc/intel/baytrail/baytrail/romstage.h
index 760905c..4918a02 100644
--- a/src/soc/intel/baytrail/baytrail/romstage.h
+++ b/src/soc/intel/baytrail/baytrail/romstage.h
@@ -48,6 +48,7 @@
 void raminit(struct mrc_params *mp, int prev_sleep_state);
 void gfx_init(void);
 void tco_disable(void);
+void punit_init(void);
 
 #if CONFIG_ENABLE_BUILTIN_COM1
 void byt_config_com1_and_enable(void);
diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c
index 414a6bb..6bd7805 100644
--- a/src/soc/intel/baytrail/romstage/pmc.c
+++ b/src/soc/intel/baytrail/romstage/pmc.c
@@ -34,3 +34,23 @@
 	outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT);
 }
 
+/* This sequence signals the PUNIT to start running. */
+void punit_init(void)
+{
+	uint32_t reg;
+
+	/* Write bits 17:16 of SB_BIOS_CONFIG in the PUNIT. */
+	reg = SB_BIOS_CONFIG_PERF_MODE | SB_BIOS_CONFIG_PDM_MODE;
+	pci_write_config32(IOSF_PCI_DEV, MDR_REG, reg);
+	reg = IOSF_OPCODE(IOSF_OP_WRITE_PMC) | IOSF_PORT(IOSF_PORT_PMC) |
+	     IOSF_REG(SB_BIOS_CONFIG) | IOSF_BYTE_EN_2;
+	pci_write_config32(IOSF_PCI_DEV, MCR_REG, reg);
+
+	/* Write bits 1:0 of BIOS_RESET_CPL in the PUNIT. */
+	reg = BIOS_RESET_CPL_ALL_DONE | BIOS_RESET_CPL_RESET_DONE;
+	pci_write_config32(IOSF_PCI_DEV, MDR_REG, reg);
+	reg = IOSF_OPCODE(IOSF_OP_WRITE_PMC) | IOSF_PORT(IOSF_PORT_PMC) |
+	     IOSF_REG(BIOS_RESET_CPL) | IOSF_BYTE_EN_0;
+	pci_write_config32(IOSF_PCI_DEV, MCR_REG, reg);
+}
+
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index dcadd91..6d28abc 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -112,6 +112,8 @@
 
 	console_init();
 
+	punit_init();
+
 	gfx_init();
 
 	mark_ts(params, timestamp_get());