| ## |
| ## This file is part of the coreboot project. |
| ## |
| ## Copyright (C) 2011 Google Inc. |
| ## |
| ## This program is free software; you can redistribute it and/or modify |
| ## it under the terms of the GNU General Public License as published by |
| ## the Free Software Foundation; version 2 of the License. |
| ## |
| ## This program is distributed in the hope that it will be useful, |
| ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| ## GNU General Public License for more details. |
| ## |
| ## You should have received a copy of the GNU General Public License |
| ## along with this program; if not, write to the Free Software |
| ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| ## |
| |
| config SOUTHBRIDGE_INTEL_LYNXPOINT |
| bool |
| |
| if SOUTHBRIDGE_INTEL_LYNXPOINT |
| |
| config SOUTH_BRIDGE_OPTIONS # dummy |
| def_bool y |
| select IOAPIC |
| select HAVE_HARD_RESET |
| select HAVE_USBDEBUG |
| select USE_WATCHDOG_ON_BOOT |
| select PCIEXP_ASPM |
| select PCIEXP_COMMON_CLOCK |
| select SPI_FLASH |
| select ALT_CBFS_LOAD_PAYLOAD |
| |
| config INTEL_LYNXPOINT_LP |
| bool |
| default n |
| help |
| Set this option to y for Lynxpont LP (Haswell ULT). |
| |
| config EHCI_BAR |
| hex |
| default 0xfef00000 |
| |
| config EHCI_DEBUG_OFFSET |
| hex |
| default 0xa0 |
| |
| config BOOTBLOCK_SOUTHBRIDGE_INIT |
| string |
| default "southbridge/intel/lynxpoint/bootblock.c" |
| |
| config SERIRQ_CONTINUOUS_MODE |
| bool |
| default n |
| help |
| If you set this option to y, the serial IRQ machine will be |
| operated in continuous mode. |
| |
| config ME_MBP_CLEAR_LATE |
| bool "Defer wait for ME MBP Cleared" |
| default y |
| help |
| If you set this option to y, the Management Engine driver |
| will defer waiting for the MBP Cleared indicator until the |
| finalize step. This can speed up boot time if the ME takes |
| a long time to indicate this status. |
| |
| config FINALIZE_USB_ROUTE_XHCI |
| bool "Route all ports to XHCI controller in finalize step" |
| default y |
| help |
| If you set this option to y, the USB ports will be routed |
| to the XHCI controller during the finalize SMM callback. |
| |
| config LOCK_MANAGEMENT_ENGINE |
| bool "Lock Management Engine section" |
| default n |
| help |
| The Intel Management Engine supports preventing write accesses |
| from the host to the Management Engine section in the firmware |
| descriptor. If the ME section is locked, it can only be overwritten |
| with an external SPI flash programmer. You will want this if you |
| want to increase security of your ROM image once you are sure |
| that the ME firmware is no longer going to change. |
| |
| If unsure, say N. |
| |
| endif |