##
## This file is part of the coreboot project.
##
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##

chip northbridge/intel/i440bx		# Northbridge
  device cpu_cluster 0 on		# APIC cluster
    chip cpu/intel/slot_1		# CPU
      device lapic 0 on end		# APIC
    end
  end
  device domain 0 on		# PCI domain
    device pci 0.0 on end		# Host bridge
    device pci 1.0 on end		# PCI/AGP bridge
    chip southbridge/intel/i82371eb	# Southbridge
      device pci 7.0 on			# ISA bridge
        chip superio/winbond/w83977tf	# Super I/O
          device pnp 3f0.0 on		# Floppy
            io 0x60 = 0x3f0
            irq 0x70 = 6
            drq 0x74 = 2
          end
          device pnp 3f0.1 on		# Parallel port
            io 0x60 = 0x378
            irq 0x70 = 7
            drq 0x74 = 3
          end
          device pnp 3f0.2 on		# COM1
            io 0x60 = 0x3f8
            irq 0x70 = 4
          end
          device pnp 3f0.3 on		# COM2 / IR
            io 0x60 = 0x2f8
            irq 0x70 = 3
          end
          device pnp 3f0.5 on		# PS/2 keyboard
            io 0x60 = 0x60
            io 0x62 = 0x64
            irq 0x70 = 1		# PS/2 keyboard interrupt
            irq 0x72 = 12		# PS/2 mouse interrupt
          end
          device pnp 3f0.7 off		# GPIO 1
          end
          device pnp 3f0.8 off		# GPIO 2
          end
          device pnp 3f0.9 off		# GPIO 3
          end
          device pnp 3f0.a off		# ACPI
          end
        end
      end
      device pci 7.1 on end		# IDE
      device pci 7.2 on end		# USB
      device pci 7.3 on end		# ACPI
      device pci 14.0 on end		# Onboard audio (Ensoniq ES1371)
      register "ide0_enable" = "1"
      register "ide1_enable" = "1"
      register "ide_legacy_enable" = "1"
      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
      register "ide0_drive0_udma33_enable" = "1"
      register "ide0_drive1_udma33_enable" = "1"
      register "ide1_drive0_udma33_enable" = "1"
      register "ide1_drive1_udma33_enable" = "1"
    end
  end
end