commit | f1d3727161ed182e34ec14b6a9ac044e6cfa1efa | [log] [tgz] |
---|---|---|
author | Ravi Kumar Bokka <rbokka@codeaurora.org> | Fri Nov 05 17:27:46 2021 +0530 |
committer | Commit Bot <commit-bot@chromium.org> | Sat Feb 12 00:15:35 2022 +0000 |
tree | 02963f9c52b04d43d28e2d7a02c5119a949044ad | |
parent | baa32f2e47ec7154ed308ef678139809aed4086f [diff] |
UPSTREAM: mb/google/herobrine: Add senor support QUP FW for I2C and SPI Add senor board to QUP FW load for: APPS I2C, ESIM SPI & fingerprint SPI. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board. (cherry picked from commit eaac053d2391d65b8e23f624c4c08a83fdbaae0f) Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Original-Change-Id: I6fdd09bb437547e6d12eb60c4b2917d2a3074618 GitOrigin-RevId: eaac053d2391d65b8e23f624c4c08a83fdbaae0f Change-Id: I68cec17c2a9c36f54ce15e0093024c39dcf1418b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3426199 Tested-by: CopyBot Service Account <copybot.service@gmail.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Andrew McRae <amcrae@google.com> Commit-Queue: Shelley Chen <shchen@chromium.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.