tree 88cfcc35d028b18809166009ca8ea8d724cafac0
parent d4e086d538bce29602ec39d06d088e949d84ae5e
author Wonkyu Kim <wonkyu.kim@intel.com> 1579914128 -0800
committer Commit Bot <commit-bot@chromium.org> 1580314412 +0000

UPSTREAM: soc/intel/tigerlake: Disable image clocks

TGL FSP does just pin mux for image clock pins by UPD and image clocks
are controlled by ACPI(camera_clock_ctl.asl) under tigerlake SOC folder.
Disable image clocks by UPD for bypassing FSP pin mux and do pin mux
in gpio.c according to board design.

BUG=none
BRANCH=none
TEST=Build and boot to OS

Change-Id: I4fb3a1ad3470eb31b1cb068cff472a1199e0d8ba
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c332a47c54f6e9b025a36e14eb0d3b115400d21c
Original-Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Original-Change-Id: I5aba5b2fb6deee231e3ec34c8dbc9972b01041f2
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/38562
Original-Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2027434
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>