##
## This file is part of the coreboot project.
##
## Copyright (C) 2019 Advanced Micro Devices, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##

config SOC_AMD_PICASSO
	bool
	help
	  AMD Picasso support

if SOC_AMD_PICASSO

config CPU_SPECIFIC_OPTIONS
	def_bool y
	select ARCH_BOOTBLOCK_X86_32
	select ARCH_VERSTAGE_X86_32
	select ARCH_ROMSTAGE_X86_32
	select ARCH_RAMSTAGE_X86_32
	select RESET_VECTOR_IN_RAM
	select X86_AMD_FIXED_MTRRS
	select X86_AMD_INIT_SIPI
	select ACPI_AMD_HARDWARE_SLEEP_VALUES
	select DRIVERS_I2C_DESIGNWARE
	select GENERIC_GPIO_LIB
	select IOAPIC
	select HAVE_USBDEBUG_OPTIONS
	select SPI_FLASH if HAVE_ACPI_RESUME
	select TSC_CONSTANT_RATE
	select TSC_MONOTONIC_TIMER
	select TSC_SYNC_LFENCE
	select UDELAY_TSC
	select COLLECT_TIMESTAMPS
	select SOC_AMD_COMMON
	select SOC_AMD_COMMON_BLOCK
	select SOC_AMD_COMMON_BLOCK_IOMMU
	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
	select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
	select SOC_AMD_COMMON_BLOCK_ACPI
	select SOC_AMD_COMMON_BLOCK_LPC
	select SOC_AMD_COMMON_BLOCK_PCI
	select SOC_AMD_COMMON_BLOCK_HDA
	select SOC_AMD_COMMON_BLOCK_SATA
	select SOC_AMD_COMMON_BLOCK_PSP
	select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
	select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
	select PARALLEL_MP
	select PARALLEL_MP_AP_WORK
	select HAVE_SMI_HANDLER
	select SSE2
	select RTC
	select PLATFORM_USES_FSP2_0
	select FSP_USES_CB_STACK
	select UDK_2017_BINDING
	select HAVE_CF9_RESET
	select HAVE_ESPI_INIT_DEBUG
	select NO_STAGE_CACHE

config VBOOT
	select VBOOT_SEPARATE_VERSTAGE
	select VBOOT_STARTS_IN_BOOTBLOCK
	select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
	select VBOOT_VBNV_CMOS
	select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH

config HAVE_BOOTBLOCK
	bool
	default n

config PRERAM_CBMEM_CONSOLE_SIZE
	hex
	default 0x1600
	help
	  Increase this value if preram cbmem console is getting truncated

config CPU_ADDR_BITS
	int
	default 48

config MMCONF_BASE_ADDRESS
	hex
	default 0xF8000000

config MMCONF_BUS_NUMBER
	int
	default 64

config VGA_BIOS_ID
	string
	default "1002,15d8,c1"
	help
	  The default VGA BIOS PCI vendor/device ID should be set to the
	  result of the map_oprom_vendev() function in northbridge.c.

config VGA_BIOS_FILE
	string
	default "3rdparty/blobs/soc/amd/picasso/PicassoGenericVbios.bin"

# Add Dali VBIOS to build
config SECOND_VBIOS
	def_bool y

config SECOND_VBIOS_ID
	string
	default "1002,15d8,c4"
	help
	  Because Dali and Picasso need different video BIOSes, but have the
	  same vendor/device IDs, we need an alternate method to determine the
	  correct video BIOS. In map_oprom_vendev(), we look at the cpuid and
	  decide which rom to load.

config SECOND_VBIOS_FILE
	string
	default "3rdparty/blobs/soc/amd/picasso/Raven2GenericVbios.bin"

config CHECK_REV_IN_OPROM_NAME
	bool
	default y
	help
	  Select this in the platform BIOS or chipset if the option rom has a
	   revision that needs to be checked when searching CBFS.

config S3_VGA_ROM_RUN
	bool
	default n

config HEAP_SIZE
	hex
	default 0xc0000

config EHCI_BAR
	hex
	default 0xfef00000

config AMD_PUBKEY_FILE
	string "AMD public Key"
	default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyRV.bin"

config SERIRQ_CONTINUOUS_MODE
	bool
	default n
	help
	  Set this option to y for serial IRQ in continuous mode.
	  Otherwise it is in quiet mode.

config PICASSO_ACPI_IO_BASE
	hex
	default 0x400
	help
	  Base address for the ACPI registers.

config PICASSO_UART
	bool "UART controller on Picasso"
	default n
	select DRIVERS_UART_8250MEM
	select DRIVERS_UART_8250MEM_32
	select NO_UART_ON_SUPERIO
	select UART_OVERRIDE_REFCLK
	help
	  There are four memory-mapped UARTs controllers in Picasso at:
	  0: 0xfedc9000
	  1: 0xfedca000
	  2: 0xfedc3000
	  3: 0xfedcf000

choice PICASSO_UART_CLOCK_SOURCE
	prompt "UART Frequency"
	depends on PICASSO_UART
	default PICASSO_UART_48MZ

config PICASSO_UART_48MZ
	bool "48 MHz clock"
	help
	  Select this option for the most compatibility.

config PICASSO_UART_1_8MZ
	bool "1.8432 MHz clock"
	help
	  Select this option if an old payload or Linux ttyS0 arguments
	  require it.

endchoice

config PICASSO_UART_LEGACY
	bool "Decode legacy I/O range"
	depends on PICASSO_UART
	help
	  Assign I/O 3F8, 2F8, etc. to a Picasso UART.  Only a single UART may
	  decode legacy addresses and this option enables the one used for the
	  console.  A UART accessed with I/O does not allow all the features
	  of MMIO.  The MMIO decode is still present when this option is used.

config CONSOLE_UART_BASE_ADDRESS
	depends on CONSOLE_SERIAL && PICASSO_UART
	hex
	default 0xfedc9000 if UART_FOR_CONSOLE = 0
	default 0xfedca000 if UART_FOR_CONSOLE = 1
	default 0xfedc3000 if UART_FOR_CONSOLE = 2
	default 0xfedcf000 if UART_FOR_CONSOLE = 3

config SMM_TSEG_SIZE
	hex
	default 0x800000 if SMM_TSEG && HAVE_SMI_HANDLER
	default 0x0

config SMM_RESERVED_SIZE
	hex
	default 0x150000

config SMM_MODULE_STACK_SIZE
	hex
	default 0x800

config ACPI_CPU_STRING
	string
	default "\\_PR.C%03d"

config ACPI_BERT
	bool "Build ACPI BERT Table"
	default y
	depends on HAVE_ACPI_TABLES
	help
	  Report Machine Check errors identified in POST to the OS in an
	  ACPI Boot Error Record Table.  This option reserves an 8MB region
	  for building the error structures.

config RO_REGION_ONLY
	string
	depends on CHROMEOS
	default "apu/amdfw"

config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
	int
	default 150

config PICASSO_LPC_IOMUX
	bool
	help
	  Picasso's LPC bus signals are MUXed with some of the EMMC signals.
	  Select this option if LPC signals are required.

config MAINBOARD_POWER_RESTORE
	def_bool n
	help
	  This option determines what state to go to once power is restored
	  after having been lost in S0.  Select this option to automatically
	  return to S0.  Otherwise the system will remain in S5 once power
	  is restored.

menu "PSP Configuration Options"

config ROMSTAGE_ADDR
	hex
	default 0x8000000
	help
	  The base address in DRAM for where the hybrid romstage is linked and
	  the destination where the PSP uncompresses the image.  The size
	  is 64KB and the reset vector is ROMSTAGE_ADDR + 0xfff0.  Systems
	  supporting S3 must reserved this region from use by the OS.

config X86_RESET_VECTOR
	hex
	depends on ARCH_X86
	default 0x807fff0
	help
	  Specify the location of the x86 reset vector.  In traditional devices
	  this must match the architectural reset vector to produce a bootable
	  image.  Nontraditional designs may use this to position the reset
	  vector into its desired location.

config RAM_RESET_VECTOR_STAGE_BSS_SIZE
	hex
	depends on RESET_VECTOR_IN_RAM
	default 0x40000
	help
	  A common region of DRAM is allocated for use as .bss for all
	  pre-ramstage stages and is located within the initial stage.

config EARLYRAM_BSP_STACK_SIZE
	hex
	default 0x1000

config FSP_TEMP_RAM_SIZE
	hex
	depends on FSP_USES_CB_STACK
	default 0x40000
	help
	  The amount of coreboot-allocated heap and stack usage by the FSP.

config EARLYRAM_AP_STACK_SIZE
	hex
	default 0x1000

config AMDFW_OUTSIDE_CBFS
	bool "The AMD firmware is outside CBFS"
	default n
	help
	  The AMDFW (PSP) is typically locatable in cbfs.  Select this
	  option to manually attach the generated amdfw.rom outside of
	  cbfs.  The location is selected by the FWM position.

config AMD_FWM_POSITION_INDEX
	int "Firmware Directory Table location (0 to 5)"
	range 0 5
	default 0 if BOARD_ROMSIZE_KB_512
	default 1 if BOARD_ROMSIZE_KB_1024
	default 2 if BOARD_ROMSIZE_KB_2048
	default 3 if BOARD_ROMSIZE_KB_4096
	default 4 if BOARD_ROMSIZE_KB_8192
	default 5 if BOARD_ROMSIZE_KB_16384
	help
	  Typically this is calculated by the ROM size, but there may
	  be situations where you want to put the firmware directory
	  table in a different location.
	    0: 512 KB - 0xFFFA0000
	    1: 1 MB   - 0xFFF20000
	    2: 2 MB   - 0xFFE20000
	    3: 4 MB   - 0xFFC20000
	    4: 8 MB   - 0xFF820000
	    5: 16 MB  - 0xFF020000

comment "AMD Firmware Directory Table set to location for 512KB ROM"
	depends on AMD_FWM_POSITION_INDEX = 0
comment "AMD Firmware Directory Table set to location for 1MB ROM"
	depends on AMD_FWM_POSITION_INDEX = 1
comment "AMD Firmware Directory Table set to location for 2MB ROM"
	depends on AMD_FWM_POSITION_INDEX = 2
comment "AMD Firmware Directory Table set to location for 4MB ROM"
	depends on AMD_FWM_POSITION_INDEX = 3
comment "AMD Firmware Directory Table set to location for 8MB ROM"
	depends on AMD_FWM_POSITION_INDEX = 4
comment "AMD Firmware Directory Table set to location for 16MB ROM"
	depends on AMD_FWM_POSITION_INDEX = 5

config AMD_PUBKEY_FILE
	string "AMD public Key"
	default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyRV.bin"

config PSP_APCB_FILE
	string "APCB file"
	help
	  The name of the AGESA Parameter Customization Block.  This image is
	  instance ID 0 in the PSP's BIOS Directory Table.

config PSP_APCB1_FILE
	string
	help
	  If specified, this image is instance ID 1 in the PSP's BIOS
	  Directory Table.

config PSP_APCB2_FILE
	string
	help
	  If specified, this image is instance ID 2 in the PSP's BIOS
	  Directory Table.

config PSP_APCB3_FILE
	string
	help
	  If specified, this image is instance ID 3 in the PSP's BIOS
	  Directory Table.

config PSP_APCB4_FILE
	string
	help
	  If specified, this image is instance ID 4 in the PSP's BIOS
	  Directory Table.

config PSP_APOB_DESTINATION
	hex
	default 0x9f00000
	help
	  Location in DRAM where the PSP will copy the AGESA PSP Output
	  Block.

config PSP_APOB_NV_ADDRESS
	hex "Base address of APOB NV"
	default 0xffa68000
	help
	  Location in flash where the PSP can find the S3 restore information.
	  Place this on a boundary that the flash device can erase.
	  TODO:  The above default value is arbitrary, but eventually coreboot's
	  MRC cache base address should be used.

config PSP_APOB_NV_SIZE
	hex "Size of APOB NV to be reserved"
	default 0x10000
	help
	  Size of the S3 restore information.  Make this a multiple of the
	  size the flash device can erase.
	  TODO:  The above default value is arbitrary, but eventually coreboot's
	  MRC cache size should be used.

config USE_PSPSCUREOS
	bool "Include PSP SecureOS blobs in PSP build"
	default y
	help
	  Include the PspSecureOs and PspTrustlet binaries in the PSP build.

	  If unsure, answer 'y'

config PSP_LOAD_MP2_FW
	bool "Include MP2 blobs in PSP build"
	default y
	help
	  Include the MP2 firmwares and configuration into the PSP build.

	  If unsure, answer 'y'

config PSP_LOAD_S0I3_FW
	bool "Include S0I3 blob in PSP build"
	help
	  Select this item to include the S0i3 file into the PSP build.

config HAVE_PSP_WHITELIST_FILE
	bool "Include a debug whitelist file in PSP build"
	default n
	help
	  Support secured unlock prior to reset using a whitelisted
	  number?  This feature requires a signed whitelist image and
	  bootloader from AMD.

	  If unsure, answer 'n'

config PSP_WHITELIST_FILE
	string "Debug whitelist file name"
	depends on HAVE_PSP_WHITELIST_FILE
	default "3rdparty/blobs/soc/amd/picasso/PSP/wtl-rvn.sbin"

endmenu

endif # SOC_AMD_PICASSO