commit | 102c5dbb1453aeefb87022ca94d4c57cbf8c8b58 | [log] [tgz] |
---|---|---|
author | Angel Pons <th3fanbus@gmail.com> | Mon Apr 19 22:31:49 2021 +0200 |
committer | Commit Bot <commit-bot@chromium.org> | Mon Jun 14 18:19:40 2021 +0000 |
tree | 0dd6212683e758de4f6e0916ae8b87737b7f1ca3 | |
parent | 662f5a58a99f89486754a16cc56e7f0b1c08e5c5 [diff] |
soc/intel/broadwell/pch: Replace ACPI device NVS The same functionality can be provided through a runtime-generated SSDT. The remaining parts of device NVS are removed in a follow-up. Since the SSDTs are only loaded after the DSDT (if loaded at all), using SSDT-provided objects outside method bodies is not possible: the objects are not yet in OSPM's ACPI namespace, which causes in ACPI errors. Owing to this, the operation regions used by the _PS0 and _PS3 methods need to be moved into the SSDT, as they depend on the SSDT-provided BAR1 values. Tested on out-of-tree Compal LA-A992P, generated SSDT disassembles with no errors and contains expected values. Linux does not complain either. Change-Id: I89fb658fbb10a8769ebea2e6535c45cd7c212d06 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2960799 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.