tree c6b07009385f0e17f672e2665bc15f7d03198a8e
parent 3ec9cb28882f8c05a728fc2b92c7bfe9863614ce
author Reka Norman <rekanorman@google.com> 1696286821 +1100
committer Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> 1706087192 +0000

UPSTREAM: util/ifdtool: Add support for disabling GPR0

On ChromeOS devices with updateable CSE firmware, the GPR0 (Global
Protected Range) register is used to ensure the CSE RO is write
protected even when the FLMSTR-based protection is temporarily disabled
by coreboot to allow updating the CSE RW. For more details see
Documentation/soc/intel/cse_fw_update/cse_fw_update.md

Therefore to allow modifying the CSE firmware from the CPU, the
descriptor must have both the FLMSTR-based protection disabled (which
can be done using ifdtool --unlock), and GPR0 disabled.

Add an ifdtool option for disabling GPR0. For now I've added support for
all platforms for which I have the SPI programming guide. Support for
more platforms can be added in the future if needed.

BUG=b:270275115
TEST=Run `ifdtool -p adl -g image.bin -O image-unlocked.bin` on a locked
craask image, check the GPR0 field is set to 0.

(cherry picked from commit c64be928de8421ea1bb2f575e32d74d58e41d659)

Original-Change-Id: Iee13ce0b702b3c7a443501cb4fc282580869d03a
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/79788
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GitOrigin-RevId: c64be928de8421ea1bb2f575e32d74d58e41d659
Change-Id: Ibe634c89eb07744bdee7e07bba5b833d11b8062f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/5173176
Commit-Queue: ChromeOS Auto Retry <chromeos-auto-retry@chromeos-bot.iam.gserviceaccount.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/5199730
Auto-Submit: Phoebe Wang <phoebewang@chromium.org>
Commit-Queue: Phoebe Wang <phoebewang@chromium.org>
Reviewed-by: Cheng Yueh <cyueh@chromium.org>
Tested-by: Phoebe Wang <phoebewang@chromium.org>