| From b6f9101aba52de945f7c115cec0e0831eea20f4e Mon Sep 17 00:00:00 2001 |
| From: Alexandre TORGUE <alexandre.torgue@st.com> |
| Date: Mon, 17 Jul 2017 13:59:16 +0200 |
| Subject: [PATCH 2/2] Add stm32h7x.cfg config file |
| |
| Change-Id: I2aae2c5acff4f3ff8e1bf232fda5a11a87f71703 |
| Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> |
| --- |
| tcl/target/stm32h7x.cfg | 152 ++++++++++++++++++++++++++++++++++++++++++++++++ |
| 1 file changed, 152 insertions(+) |
| create mode 100644 tcl/target/stm32h7x.cfg |
| |
| diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg |
| new file mode 100644 |
| index 00000000..a50d956f |
| --- /dev/null |
| +++ b/tcl/target/stm32h7x.cfg |
| @@ -0,0 +1,152 @@ |
| +# script for stm32h7x family |
| + |
| +# |
| +# stm32h7 devices support both JTAG and SWD transports. |
| +# |
| +source [find target/swj-dp.tcl] |
| +source [find mem_helper.tcl] |
| + |
| +if { [info exists CHIPNAME] } { |
| + set _CHIPNAME $CHIPNAME |
| +} else { |
| + set _CHIPNAME stm32h7x |
| +} |
| + |
| +set _ENDIAN little |
| + |
| +# Work-area is a space in RAM used for flash programming |
| +# By default use 64kB |
| +if { [info exists WORKAREASIZE] } { |
| + set _WORKAREASIZE $WORKAREASIZE |
| +} else { |
| + set _WORKAREASIZE 0x10000 |
| +} |
| + |
| +#jtag scan chain |
| +if { [info exists CPUTAPID] } { |
| + set _CPUTAPID $CPUTAPID |
| +} else { |
| + if { [using_jtag] } { |
| + set _CPUTAPID 0x6ba00477 |
| + } { |
| + set _CPUTAPID 0x6ba02477 |
| + } |
| +} |
| + |
| +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID |
| + |
| +if { [info exists BSTAPID] } { |
| + set _BSTAPID1 $BSTAPID |
| +} else { |
| + # See STM Document RM0399 |
| + # Section 40.6.1 |
| + # STM32H74xxI |
| + set _BSTAPID1 0x06450041 |
| +} |
| + |
| +if {[using_jtag]} { |
| + swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 |
| +} |
| + |
| +set _TARGETNAME $_CHIPNAME.cpu |
| +target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME |
| + |
| +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 |
| + |
| +set _FLASHNAME $_CHIPNAME.flash |
| +flash bank $_FLASHNAME stm32h7x 0x08000000 0 0 0 $_TARGETNAME |
| + |
| +# check for second flash bank |
| +if { [regexp -nocase {stm32h74..i..|stm32h75..i..} $_CHIPNAME] } { |
| + # STM32H7xxxI 2Mo have a dual bank flash. |
| + # Add the second flash bank. |
| + set _FLASHNAME $_CHIPNAME.flash1 |
| + flash bank $_FLASHNAME stm32h7x 0x08100000 0 0 0 $_TARGETNAME |
| +} |
| + |
| + |
| +# Clock after reset is HSI at 64 MHz, no need of PLL |
| +if { [info exists CLOCK_FREQ] } { |
| + set _CLOCK_FREQ $CLOCK_FREQ |
| +} else { |
| + set _CLOCK_FREQ 1800 |
| +} |
| +adapter_khz 1800 |
| + |
| + |
| +adapter_nsrst_delay 100 |
| +if {[using_jtag]} { |
| + jtag_ntrst_delay 100 |
| +} |
| + |
| +if {![using_hla]} { |
| + # if srst is not fitted use SYSRESETREQ to |
| + # perform a soft reset |
| + cortex_m reset_config sysresetreq |
| +} |
| + |
| +$_TARGETNAME configure -event trace-config { |
| + # Set TRACE_CLKEN; TRACE_MODE is set to async; when using sync |
| + # change this value accordingly to configure trace pins |
| + # assignment |
| + mmw 0x5C001004 0x00100000 0 |
| +} |
| + |
| +$_TARGETNAME configure -event reset-init { |
| +global ENABLE_LOW_POWER |
| +global STOP_WATCHDOG |
| +global _CLOCK_FREQ |
| + |
| + # Not done in target examine-end because device can be under reset and we get comm errors |
| + |
| + # Enable D3 and D1 DBG clocks |
| + # DBGMCU_CR |= DBG_CKEN_D3 | DBG_CKEN_D1 |
| + mmw 0x5C001004 0x00600000 0 |
| + |
| + if { [expr ($ENABLE_LOW_POWER == 1)] } { |
| + # Enable debug during low power modes (uses more power) |
| + # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3, D2 & D1 Domains |
| + mmw 0x5C001004 0x000001BF 0 |
| + } |
| + if { [expr ($ENABLE_LOW_POWER == 0)] } { |
| + # Disable debug during low power modes |
| + # DBGMCU_CR |= ~(DBG_STANDBY | DBG_STOP | DBG_SLEEP) |
| + mmw 0x5C001004 0 0x000001BF |
| + } |
| + if { [expr ($STOP_WATCHDOG == 1)] } { |
| + # Stop watchdog counters during halt |
| + # DBGMCU_D1APB1_FZ |= DBG_WWDG1_STOP |
| + mmw 0x5C001034 0x00000040 0 |
| + # DBGMCU_D2APB1_FZ |= DBG_WWDG2_STOP |
| + mmw 0x5C00103C 0x00000800 0 |
| + # DBGMCU_D3APB1_FZ |= DBG_WDGLSD2_STOP | DBG_WDGLSD1_STOP |
| + mmw 0x5C001054 0x000C0000 0 |
| + } |
| + if { [expr ($STOP_WATCHDOG == 0)] } { |
| + # Don't stop watchdog counters during halt |
| + # DBGMCU_D1APB1_FZ |= ~DBG_WWDG1_STOP |
| + mmw 0x5C001034 0 0x00000040 |
| + # DBGMCU_D2APB1_FZ |= ~DBG_WWDG2_STOP |
| + mmw 0x5C00103C 0 0x00000800 |
| + # DBGMCU_D3APB1_FZ |= ~(DBG_WDGLSD2_STOP | DBG_WDGLSD1_STOP) |
| + mmw 0x5C001054 0 0x000C0000 |
| + } |
| + if { [expr ($ENABLE_LOW_POWER == 0)] && [expr ($STOP_WATCHDOG == 0)] } { |
| + # Disable D3 and D1 DBG clocks |
| + # DBGMCU_CR |= ~(DBG_CKEN_D3 | DBG_CKEN_D1) |
| + mmw 0x5C001004 0 0x00600000 |
| + } |
| + |
| + # Clock after reset is HSI at 64 MHz, no need of PLL |
| + adapter_khz $_CLOCK_FREQ |
| +} |
| + |
| +$_TARGETNAME configure -event gdb-attach { |
| +global CONNECT_UNDER_RESET |
| + |
| + # Needed to be able to use the connect_assert_srst in reset_config |
| + # otherwise, can't read device flash size register |
| + if { [expr ($CONNECT_UNDER_RESET == 1)] } { |
| + reset init |
| + } |
| +} |
| -- |
| 2.14.1.821.g8fa685d3b7-goog |
| |
