| # Copyright (c) 2013 The Chromium OS Authors. All rights reserved. |
| # Distributed under the terms of the GNU General Public License v2 |
| |
| # Do not edit. Generated by T40_emc_reg_tool4.1.7 V4.1.7. Command: |
| # T40_emc_reg_tool4.1.7 -i Hynix_1GB_H5TC4G63AFR-PBA_ddr3_1600_060413.par -b emc_reg_792.txt 1.262626 |
| # -s chrome_0612_emc_reg_swz.txt -o PM335_792.cfg -dram_board_cfg 6 -fly_by_time_ps 2925 |
| # -for_boot 1 -pllm_ref_khz 12000 |
| # Parameter file: Hynix_1GB_H5TC4G63AFR-PBA_ddr3_1600_060413.par, tck = 1.26 ns (792.00 MHz) |
| # bkv file: emc_reg_792.txt |
| # swz file: chrome_0612_emc_reg_swz.txt |
| SDRAM[0].MemoryType = NvBootMemoryType_Ddr3; |
| SDRAM[0].PllMInputDivider = 0x00000001; |
| SDRAM[0].PllMFeedbackDivider = 0x00000042; |
| SDRAM[0].PllMStableTime = 0x0000012c; |
| SDRAM[0].PllMSetupControl = 0x00000000; |
| SDRAM[0].PllMSelectDiv2 = 0x00000000; |
| SDRAM[0].PllMPDLshiftPh45 = 0x00000001; |
| SDRAM[0].PllMPDLshiftPh90 = 0x00000001; |
| SDRAM[0].PllMPDLshiftPh135 = 0x00000001; |
| SDRAM[0].PllMKCP = 0x00000000; |
| SDRAM[0].PllMKVCO = 0x00000000; |
| SDRAM[0].EmcBctSpare0 = 0x00000bad; |
| SDRAM[0].EmcClockSource = 0x84000000; |
| SDRAM[0].EmcAutoCalInterval = 0x001fffff; |
| SDRAM[0].EmcAutoCalConfig = 0xa0f10f0f; |
| SDRAM[0].EmcAutoCalConfig2 = 0x00000000; |
| SDRAM[0].EmcAutoCalConfig3 = 0x00000000; |
| SDRAM[0].EmcAutoCalWait = 0x00000064; |
| SDRAM[0].EmcAdrCfg = 0x00000000; |
| SDRAM[0].EmcPinProgramWait = 0x00000001; |
| SDRAM[0].EmcPinExtraWait = 0x00000000; |
| SDRAM[0].EmcTimingControlWait = 0x00000001; |
| SDRAM[0].EmcRc = 0x00000025; |
| SDRAM[0].EmcRfc = 0x000000cc; |
| SDRAM[0].EmcRfcSlr = 0x00000000; |
| SDRAM[0].EmcRas = 0x0000001a; |
| SDRAM[0].EmcRp = 0x00000009; |
| SDRAM[0].EmcR2r = 0x00000000; |
| SDRAM[0].EmcW2w = 0x00000000; |
| SDRAM[0].EmcR2w = 0x00000008; |
| SDRAM[0].EmcW2r = 0x0000000d; |
| SDRAM[0].EmcR2p = 0x00000004; |
| SDRAM[0].EmcW2p = 0x00000013; |
| SDRAM[0].EmcRdRcd = 0x00000009; |
| SDRAM[0].EmcWrRcd = 0x00000009; |
| SDRAM[0].EmcRrd = 0x00000003; |
| SDRAM[0].EmcRext = 0x00000001; |
| SDRAM[0].EmcWext = 0x00000000; |
| SDRAM[0].EmcWdv = 0x00000006; |
| SDRAM[0].EmcWdvMask = 0x0000000f; |
| SDRAM[0].EmcQUse = 0x0000000a; |
| SDRAM[0].EmcIbdly = 0x0000000b; |
| SDRAM[0].EmcEInput = 0x00000008; |
| SDRAM[0].EmcEInputDuration = 0x00000006; |
| SDRAM[0].EmcPutermExtra = 0x00010000; |
| SDRAM[0].EmcCdbCntl1 = 0x00000000; |
| SDRAM[0].EmcCdbCntl2 = 0x00000000; |
| SDRAM[0].EmcQRst = 0x00000008; |
| SDRAM[0].EmcQSafe = 0x0000000d; |
| SDRAM[0].EmcRdv = 0x00000014; |
| SDRAM[0].EmcRdvMask = 0x00000016; |
| SDRAM[0].EmcCtt = 0x00000000; |
| SDRAM[0].EmcCttDuration = 0x00000000; |
| SDRAM[0].EmcRefresh = 0x000017e1; |
| SDRAM[0].EmcBurstRefreshNum = 0x00000000; |
| SDRAM[0].EmcPreRefreshReqCnt = 0x000005f8; |
| SDRAM[0].EmcPdEx2Wr = 0x00000003; |
| SDRAM[0].EmcPdEx2Rd = 0x00000011; |
| SDRAM[0].EmcPChg2Pden = 0x00000001; |
| SDRAM[0].EmcAct2Pden = 0x00000000; |
| SDRAM[0].EmcAr2Pden = 0x000000c6; |
| SDRAM[0].EmcRw2Pden = 0x00000018; |
| SDRAM[0].EmcTxsr = 0x000000d6; |
| SDRAM[0].EmcTxsrDll = 0x00000200; |
| SDRAM[0].EmcTcke = 0x00000005; |
| SDRAM[0].EmcTckesr = 0x00000005; |
| SDRAM[0].EmcTpd = 0x00000005; |
| SDRAM[0].EmcTfaw = 0x00000020; |
| SDRAM[0].EmcTrpab = 0x00000000; |
| SDRAM[0].EmcTClkStable = 0x00000007; |
| SDRAM[0].EmcTClkStop = 0x00000008; |
| SDRAM[0].EmcTRefBw = 0x00001822; |
| SDRAM[0].EmcQUseExtra = 0x00000000; |
| SDRAM[0].EmcFbioCfg5 = 0x00005088; |
| SDRAM[0].EmcFbioCfg6 = 0x00000006; |
| SDRAM[0].EmcFbioSpare = 0x02000000; |
| SDRAM[0].EmcCfgRsv = 0xff00ff00; |
| SDRAM[0].EmcMrs = 0x80000d71; |
| SDRAM[0].EmcEmrs = 0x80100002; |
| SDRAM[0].EmcEmrs2 = 0x80200418; |
| SDRAM[0].EmcEmrs3 = 0x80300000; |
| SDRAM[0].EmcMrw1 = 0x00000000; |
| SDRAM[0].EmcMrw2 = 0x00000000; |
| SDRAM[0].EmcMrw3 = 0x00000000; |
| SDRAM[0].EmcMrw4 = 0x00000000; |
| SDRAM[0].EmcMrwExtra = 0x00000000; |
| SDRAM[0].EmcWarmBootMrwExtra = 0x00000000; |
| SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000; |
| SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000; |
| SDRAM[0].EmcMrwResetCommand = 0x00000000; |
| SDRAM[0].EmcMrwResetNInitWait = 0x00000000; |
| SDRAM[0].EmcMrsWaitCnt = 0x00f8000c; |
| SDRAM[0].EmcMrsWaitCnt2 = 0x00f8000c; |
| SDRAM[0].EmcCfg = 0x53000000; |
| SDRAM[0].EmcCfg2 = 0x008008c5; |
| SDRAM[0].EmcDbg = 0x01000400; |
| SDRAM[0].EmcCmdQ = 0x10004408; |
| SDRAM[0].EmcMc2EmcQ = 0x06000404; |
| SDRAM[0].EmcDynSelfRefControl = 0x80003012; |
| SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001; |
| SDRAM[0].EmcCfgDigDll = 0xf0070191; |
| SDRAM[0].EmcCfgDigDllPeriod = 0x00008000; |
| SDRAM[0].EmcDevSelect = 0x00000002; |
| SDRAM[0].EmcSelDpdCtrl = 0x00040000; |
| SDRAM[0].EmcDllXformDqs0 = 0x00000008; |
| SDRAM[0].EmcDllXformDqs1 = 0x00000008; |
| SDRAM[0].EmcDllXformDqs2 = 0x00000008; |
| SDRAM[0].EmcDllXformDqs3 = 0x00000008; |
| SDRAM[0].EmcDllXformDqs4 = 0x00000008; |
| SDRAM[0].EmcDllXformDqs5 = 0x00000008; |
| SDRAM[0].EmcDllXformDqs6 = 0x00000008; |
| SDRAM[0].EmcDllXformDqs7 = 0x00000008; |
| SDRAM[0].EmcDllXformQUse0 = 0x00018000; |
| SDRAM[0].EmcDllXformQUse1 = 0x00018000; |
| SDRAM[0].EmcDllXformQUse2 = 0x00018000; |
| SDRAM[0].EmcDllXformQUse3 = 0x00018000; |
| SDRAM[0].EmcDllXformQUse4 = 0x00018000; |
| SDRAM[0].EmcDllXformQUse5 = 0x00018000; |
| SDRAM[0].EmcDllXformQUse6 = 0x00018000; |
| SDRAM[0].EmcDllXformQUse7 = 0x00018000; |
| SDRAM[0].EmcDllXformAddr0 = 0x00004000; |
| SDRAM[0].EmcDllXformAddr1 = 0x00000000; |
| SDRAM[0].EmcDllXformAddr2 = 0x00004000; |
| SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000; |
| SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000; |
| SDRAM[0].EmcDllXformDq0 = 0x0000000a; |
| SDRAM[0].EmcDllXformDq1 = 0x0000000a; |
| SDRAM[0].EmcDllXformDq2 = 0x0000000a; |
| SDRAM[0].EmcDllXformDq3 = 0x0000000a; |
| SDRAM[0].WarmBootWait = 0x00000002; |
| SDRAM[0].EmcCttTermCtrl = 0x00000802; |
| SDRAM[0].EmcOdtWrite = 0x80000000; |
| SDRAM[0].EmcOdtRead = 0x00000000; |
| SDRAM[0].EmcZcalInterval = 0x00020000; |
| SDRAM[0].EmcZcalWaitCnt = 0x00000042; |
| SDRAM[0].EmcZcalMrwCmd = 0x80000000; |
| SDRAM[0].EmcMrsResetDll = 0x00000000; |
| SDRAM[0].EmcZcalInitDev0 = 0x80000011; |
| SDRAM[0].EmcZcalInitDev1 = 0x00000000; |
| SDRAM[0].EmcZcalInitWait = 0x00000001; |
| SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003; |
| SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x000a00ab; |
| SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000011; |
| SDRAM[0].EmcZcalWarmBootWait = 0x00000001; |
| SDRAM[0].EmcMrsWarmBootEnable = 0x00000001; |
| SDRAM[0].EmcMrsResetDllWait = 0x00000000; |
| SDRAM[0].EmcMrsExtra = 0x80000d71; |
| SDRAM[0].EmcWarmBootMrsExtra = 0x80100002; |
| SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000; |
| SDRAM[0].EmcMrsDdr2DllReset = 0x00000000; |
| SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000; |
| SDRAM[0].EmcDdr2Wait = 0x00000000; |
| SDRAM[0].EmcClkenOverride = 0x00000000; |
| SDRAM[0].EmcExtraRefreshNum = 0x00000002; |
| SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000; |
| SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000; |
| SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003; |
| SDRAM[0].PmcVddpSel = 0x00000002; |
| SDRAM[0].PmcDdrPwr = 0x00000003; |
| SDRAM[0].PmcDdrCfg = 0x00000092; |
| SDRAM[0].PmcIoDpdReq = 0x80800000; |
| SDRAM[0].PmcIoDpd2Req = 0x00000000; |
| SDRAM[0].PmcRegShort = 0x00000000; |
| SDRAM[0].PmcENoVttGen = 0x00000000; |
| SDRAM[0].PmcNoIoPower = 0x00000000; |
| SDRAM[0].EmcXm2CmdPadCtrl = 0x001112a0; |
| SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000; |
| SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000; |
| SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000; |
| SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414; |
| SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0000013d; |
| SDRAM[0].EmcXm2DqsPadCtrl3 = 0x20820800; |
| SDRAM[0].EmcXm2DqsPadCtrl4 = 0x00249249; |
| SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990; |
| SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000; |
| SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc085; |
| SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000000; |
| SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108; |
| SDRAM[0].EmcXm2VttGenPadCtrl = 0x07077504; |
| SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x00000000; |
| SDRAM[0].EmcAcpdControl = 0x00000000; |
| SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00000087; |
| SDRAM[0].EmcSwizzleRank0Byte0 = 0x57624103; |
| SDRAM[0].EmcSwizzleRank0Byte1 = 0x27053614; |
| SDRAM[0].EmcSwizzleRank0Byte2 = 0x40567132; |
| SDRAM[0].EmcSwizzleRank0Byte3 = 0x45320716; |
| SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00000087; |
| SDRAM[0].EmcSwizzleRank1Byte0 = 0x57624103; |
| SDRAM[0].EmcSwizzleRank1Byte1 = 0x27053614; |
| SDRAM[0].EmcSwizzleRank1Byte2 = 0x40567132; |
| SDRAM[0].EmcSwizzleRank1Byte3 = 0x45320716; |
| SDRAM[0].EmcAddrSwizzleStack1a = 0x0396071a; |
| SDRAM[0].EmcAddrSwizzleStack1b = 0x000425b8; |
| SDRAM[0].EmcAddrSwizzleStack2a = 0x07412306; |
| SDRAM[0].EmcAddrSwizzleStack2b = 0x00000598; |
| SDRAM[0].EmcAddrSwizzleStack3 = 0x00534012; |
| SDRAM[0].EmcDsrVttgenDrv = 0x0000003f; |
| SDRAM[0].EmcTxdsrvttgen = 0x00000000; |
| SDRAM[0].McEmemAdrCfg = 0x00000000; |
| SDRAM[0].McEmemAdrCfgDev0 = 0x00080303; |
| SDRAM[0].McEmemAdrCfgDev1 = 0x00080303; |
| SDRAM[0].McEmemAdrCfgChannelMask = 0x00000640; |
| SDRAM[0].McEmemAdrCfgChannelMaskPropagationCount = 0x00000008; |
| SDRAM[0].McEmemAdrCfgBankMask0 = 0x69248003; |
| SDRAM[0].McEmemAdrCfgBankMask1 = 0x24928000; |
| SDRAM[0].McEmemAdrCfgBankMask2 = 0x92c94c00; |
| SDRAM[0].McEmemCfg = 0x00000800; |
| SDRAM[0].McEmemArbCfg = 0x0e00000b; |
| SDRAM[0].McEmemArbOutstandingReq = 0x80000190; |
| SDRAM[0].McEmemArbTimingRcd = 0x00000004; |
| SDRAM[0].McEmemArbTimingRp = 0x00000005; |
| SDRAM[0].McEmemArbTimingRc = 0x00000013; |
| SDRAM[0].McEmemArbTimingRas = 0x0000000c; |
| SDRAM[0].McEmemArbTimingFaw = 0x0000000f; |
| SDRAM[0].McEmemArbTimingRrd = 0x00000002; |
| SDRAM[0].McEmemArbTimingRap2Pre = 0x00000003; |
| SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000c; |
| SDRAM[0].McEmemArbTimingR2R = 0x00000002; |
| SDRAM[0].McEmemArbTimingW2W = 0x00000002; |
| SDRAM[0].McEmemArbTimingR2W = 0x00000006; |
| SDRAM[0].McEmemArbTimingW2R = 0x00000008; |
| SDRAM[0].McEmemArbDaTurns = 0x08060202; |
| SDRAM[0].McEmemArbDaCovers = 0x00160d13; |
| SDRAM[0].McEmemArbMisc0 = 0x734c2414; |
| SDRAM[0].McEmemArbMisc1 = 0x78000000; |
| SDRAM[0].McEmemArbRing1Throttle = 0x001f0000; |
| SDRAM[0].McEmemArbOverride = 0x00000083; |
| SDRAM[0].McEmemArbRsv = 0xff00ff00; |
| SDRAM[0].McClkenOverride = 0x00000000; |
| SDRAM[0].McEmcRegMode = 0x00000002; |
| SDRAM[0].McVideoProtectBom = 0xfff00000; |
| SDRAM[0].McVideoProtectSizeMb = 0x00000000; |
| SDRAM[0].McVideoProtectVprOverride = 0x009a4752; |
| SDRAM[0].McSecCarveoutBom = 0xfff00000; |
| SDRAM[0].McSecCarveoutSizeMb = 0x00000000; |
| SDRAM[0].McVideoProtectWriteAccess = 0x00000000; |
| SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000; |
| SDRAM[0].EmcCaTrainingEnable = 0x00000000; |
| SDRAM[0].EmcCaTrainingTimingCntl1 = 0x1f7df7df; |
| SDRAM[0].EmcCaTrainingTimingCntl2 = 0x0000001f; |
| SDRAM[0].SwizzleRankByteEncode = 0x000022aa; |
| SDRAM[0].BootRomPatchControl = 0x00000000; |
| SDRAM[0].BootRomPatchData = 0x00000000; |
| SDRAM[0].Ch1EmcDllXformDqs0 = 0x00000008; |
| SDRAM[0].Ch1EmcDllXformDqs1 = 0x00000008; |
| SDRAM[0].Ch1EmcDllXformDqs2 = 0x00000008; |
| SDRAM[0].Ch1EmcDllXformDqs3 = 0x00000008; |
| SDRAM[0].Ch1EmcDllXformDqs4 = 0x00000008; |
| SDRAM[0].Ch1EmcDllXformDqs5 = 0x00000008; |
| SDRAM[0].Ch1EmcDllXformDqs6 = 0x00000008; |
| SDRAM[0].Ch1EmcDllXformDqs7 = 0x00000008; |
| SDRAM[0].Ch1EmcDllXformQUse0 = 0x00018000; |
| SDRAM[0].Ch1EmcDllXformQUse1 = 0x00018000; |
| SDRAM[0].Ch1EmcDllXformQUse2 = 0x00018000; |
| SDRAM[0].Ch1EmcDllXformQUse3 = 0x00018000; |
| SDRAM[0].Ch1EmcDllXformQUse4 = 0x00018000; |
| SDRAM[0].Ch1EmcDllXformQUse5 = 0x00018000; |
| SDRAM[0].Ch1EmcDllXformQUse6 = 0x00018000; |
| SDRAM[0].Ch1EmcDllXformQUse7 = 0x00018000; |
| SDRAM[0].Ch1EmcDliTrimTxDqs0 = 0x00000000; |
| SDRAM[0].Ch1EmcDliTrimTxDqs1 = 0x00000000; |
| SDRAM[0].Ch1EmcDliTrimTxDqs2 = 0x00000000; |
| SDRAM[0].Ch1EmcDliTrimTxDqs3 = 0x00000000; |
| SDRAM[0].Ch1EmcDliTrimTxDqs4 = 0x00000000; |
| SDRAM[0].Ch1EmcDliTrimTxDqs5 = 0x00000000; |
| SDRAM[0].Ch1EmcDliTrimTxDqs6 = 0x00000000; |
| SDRAM[0].Ch1EmcDliTrimTxDqs7 = 0x00000000; |
| SDRAM[0].Ch1EmcDllXformDq0 = 0x0000000a; |
| SDRAM[0].Ch1EmcDllXformDq1 = 0x0000000a; |
| SDRAM[0].Ch1EmcDllXformDq2 = 0x0000000a; |
| SDRAM[0].Ch1EmcDllXformDq3 = 0x0000000a; |
| SDRAM[0].Ch1EmcSwizzleRank0ByteCfg = 0x000000d2; |
| SDRAM[0].Ch1EmcSwizzleRank0Byte0 = 0x47620153; |
| SDRAM[0].Ch1EmcSwizzleRank0Byte1 = 0x14036527; |
| SDRAM[0].Ch1EmcSwizzleRank0Byte2 = 0x72645013; |
| SDRAM[0].Ch1EmcSwizzleRank0Byte3 = 0x31520467; |
| SDRAM[0].Ch1EmcSwizzleRank1ByteCfg = 0x000000d2; |
| SDRAM[0].Ch1EmcSwizzleRank1Byte0 = 0x47620153; |
| SDRAM[0].Ch1EmcSwizzleRank1Byte1 = 0x14036527; |
| SDRAM[0].Ch1EmcSwizzleRank1Byte2 = 0x72645013; |
| SDRAM[0].Ch1EmcSwizzleRank1Byte3 = 0x31520467; |
| SDRAM[0].Ch1EmcAddrSwizzleStack1a = 0x79320a61; |
| SDRAM[0].Ch1EmcAddrSwizzleStack1b = 0x000b8450; |
| SDRAM[0].Ch1EmcAddrSwizzleStack2a = 0x07623014; |
| SDRAM[0].Ch1EmcAddrSwizzleStack2b = 0x00000589; |
| SDRAM[0].Ch1EmcAddrSwizzleStack3 = 0x00530124; |
| SDRAM[0].Ch1EmcAutoCalConfig = 0xa8f10f0f; |
| SDRAM[0].Ch1EmcAutoCalConfig2 = 0x00000000; |
| SDRAM[0].Ch1EmcAutoCalConfig3 = 0x00000000; |
| SDRAM[0].Ch1EmcCdbCntl1 = 0x00000000; |
| SDRAM[0].Ch1EmcDllXformAddr0 = 0x00004000; |
| SDRAM[0].Ch1EmcDllXformAddr1 = 0x00000000; |
| SDRAM[0].Ch1EmcDllXformAddr2 = 0x00004000; |
| SDRAM[0].Ch1EmcFbioSpare = 0x02000000; |
| SDRAM[0].Ch1EmcXm2ClkPadCtrl = 0x77ffc085; |
| SDRAM[0].Ch1EmcXm2ClkPadCtrl2 = 0x00000000; |
| SDRAM[0].Ch1EmcXm2CmdPadCtrl2 = 0x770c0000; |
| SDRAM[0].Ch1EmcXm2CmdPadCtrl3 = 0x050c0000; |
| SDRAM[0].Ch1EmcXm2CmdPadCtrl4 = 0x00000000; |
| SDRAM[0].Ch1EmcXm2DqPadCtrl = 0x770c2990; |
| SDRAM[0].Ch1EmcXm2DqPadCtrl2 = 0x00000000; |
| SDRAM[0].Ch1EmcXm2DqsPadCtrl = 0x770c1414; |
| SDRAM[0].Ch1EmcXm2DqsPadCtrl3 = 0x20820800; |
| SDRAM[0].Ch1EmcXm2DqsPadCtrl4 = 0x00249249; |